United States

Assessment of transistor degradation in analog circuits during aging effect is challenging due to wide spread of operating points. This paper presents our proposed characterization approaches of full ID-VG
degradation for large and nanoscale devices respectively. Threshold voltage shift and mobility degradation in large devices can be extracted simultaneously with fast measurement speed (tm=3us). Based on this, full ID-VG
degradation can be assessed intuitively. Impacts of individual defects on full ID-VG degradation in nanoscale devices are characterized with the proposed approach with high resolution. Thus this paper provides a helpful solution to the characterization of device degradation in analog circuits.

IRPS 2022 Main Conference 

Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

CV characteristics of MOS capacitors are classically measured in a few seconds using a capacimeter. Yet it limits the range of useful characterization that can be performed on these devices. For instance BTI reliability characterization is limited by the unavoidable recovery during every measurement step. Likewise, it is almost impossible to characterize properly the hysteresis effect present in some oxides.  Therefore we propose new ultra-fast and powerful CV techniques for MOScap, able to overcome the time limitations of former techniques.


Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

Deep level effects and on-wafer reliability have been evaluated in 0.15 mm AlGaN/GaN HEMTs differing for buffer compensation (C or Fe) and for epitaxial structure (C-doped monolayer devices with only C-doped region; C-doped bilayer samples with a barrier between the channel and the C-doped region). In monolayer devices trapping effects lead to the presence of a long time constant (50s) in drain current transients, related to the presence of CN defects; interaction with deep levels in C-doped buffer leads to knee voltage walkout, Ron increase and recoverable IDS degradation. Negative trapped charge in the gate-drain region reduces the electric field with respect to bilayer devices. Results from semi-on and on-state step stress show that by using a ‘Bi-layer’ AlGaN barrier, the interaction between C-related deep levels and channel hot electrons can be effectively reduced, thus alleviating trapping effects and parametric degradation, and giving the opportunity of fully exploiting the improved confinement offered by the C-doped buffer, at the expenses of a tolerable decrease of breakdown voltage.


Deep level effects and degradation of 0.15 um RF AlGaN/GaN HEMTs with Mono-layer and Bi-layer AlGaN backbarrier

This paper proposes an accelerator-based neutron beam to evaluate thermal-neutron-induced soft-error rate (tnSER) in semiconductor devices. The thermal-neutron flux is sufficient for the tnSER evaluation in the beam, and the moderator for the beam is compact, and we can perform the tnSER test at many facilities. We have evaluated tnSER in an SRAM with the proposed beam and a nuclear reactor, the tnSER is in good agreement between the tests with the proposed neutron beam and the nuclear reactor. 

Accelerator-Based Thermal-Neutron Beam by Compact and Low-Cost Moderator for Soft-Error Evaluation in Semiconductor Devices

We show our attempt to design space-grade low-power CMOS LSIs enhanced by magnetic tunnel junctions (MTJs). The validity is discussed by using high-energy heavy-ion experiments and macrospin simulations combined with single-event transient noise current modeling. Possible latent damage induced by heavy ions are also explored.

Design and Heavy-Ion Testing of MTJ/CMOS Hybrid LSIs for Space-Grade Soft-Error Reliability

Time and drain bias dependence of HCD under peak ISUB (VG ~ VD/2) stress are modeled. Published n-MOSFET data for different LCH (2.0µm to 37nm), TOX (35nm to 1.85nm), type of junction (HDD, LDD/HDD, SDE/HDD) and stress VD (8V to 1.6V) are analyzed. A compact model is used to model the time kinetics and to explain its difference (i.e., power law or non-power law) in devices having different types of junctions. The dominant energy model is used for VD dependence, and the model parameters are obtained with scaling. The time kinetics and VD dependence are also modeled using TCAD simulations.

Modeling Time and Bias Dependence of Classical HCD Mechanism (Peak ISUB Stress) in n-MOSFETs

It is well-known that power devices used in high-energy physics and space applications are often subjected to high amounts of radiation. Therefore, it is essential to accurately predict the long-term degradation of these power devices in the presence of radiation. In this paper, we expose LDMOS transistors to various TID of gamma radiation, quantify the dose-dependent generation of interface traps and trapped charges using a novel charge pumping technique; and establish the universality of the degradation kinetics, and illustrate that the model and inferences drawn from the findings in this paper can be applied to other LDMOS devices as well.


Correlated Effects of Radiation and Hot Carrier Degradation on the Performance of LDMOS Transistors

  DRAM vendors today choose to keep the internal topologies of DRAM devices secret.  This decision introduces significant practical challenges for designers of memory controllers who wish to provide their own forms of Rowhammer defenses. This paper describes three such challenges and the vulnerabilities, inefficiencies, and overhead they introduce. Defenses implemented at the memory controller could reduce (if not eliminate) these deficiencies should internal DRAM topology be made available.

The Price of Secrecy: How Hiding Internal DRAM Topologies Hurts Rowhammer Defenses

A comprehensive study of electric field (E-field) dependent endurance on Hf-based ferroelectric (FE) fatigue and breakdown mechanism is presented in this study. Under low E-field, reducing E-field worsens FE fatigue and constrains endurance but with no SILC increase as the result of the domain pinning. While under the high E-field stress, endurance is dominated by the field accelerated breakdown due to the increase of oxygen vacancy generation. By utilizing these distinct FE fatigue characteristics under different bias, the recoverable fatigue and prolonged cycle-to-breakdown is observed through a promising high frequency mixed-signal E-field operation.

The Field-dependence Endurance Model and Its Mutual Effect in Hf-based Ferroelectrics

The demand for high-performance computation continues to accelerate. To satisfy this increasing demand, modern server and high-performance computing systems are increasingly deploying nodes with greater heterogeneity and integration. Both trends reduce the cost of computation: heterogeneity by increasing absolute performance, and integration by reducing cost per computation. What has not changed, however, are the stringent reliability, availability, and serviceability (RAS) requirements for nodes used in server and high-performance computing systems. A high level of RAS is required to ensure that data centers deploying nodes can correctly perform computations over their expected lifetime.This paper describes the increased RAS challenges posed by increased heterogeneity and integration. The paper motivates these challenges using data gathered from production systems and presents a case study of the RAS implementation on a highly integrated, heterogeneous node: the AMD EPYC™ and AMD Instinct™ MI250X heterogeneous compute node. Finally, the paper provides a call for standardization to aid in meeting these goals for future data centers.

Reliability, Availability, and Serviceability Challenges for Heterogeneous System Design

In this study, we report an ultra-fast C-V (&gt;4 GHz) measurement methodology for characterizing the high-frequency polarization phenomena in high-k dielectric films. Both HfO2
and Al2O3 films show a significant permittivity decrease under GHz frequencies due to the suppression of ionic polarization. It is the first direct observation of separating ionic and electronic polarization in ultra-thin high-k dielectric films, so far. The phenomena found in this study could be very important for understanding relative physical mechanisms in advanced electron devices, such as ferroelectric and analog devices using high-k dielectric films.

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Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

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