United States

Periphery pFETs fabricated with the sub-20nm technology are investigated under hot carrier stress conditions when the gate voltage (|Vg|) is lower than the drain voltage (|Vd|). Two types of defects are identified: the donor-like interface trap generation causes the positive charge formation while the electron trapping in oxide traps leads to the negative charge accumulation. The corresponding energy and spatial locations are identified by analyzing the defect-induced mobility degradation and the recovery characteristic. Finally, a defect-based model is proposed for both the threshold voltage shift and the mobility degradation, which allows the prediction of the full IV after aging. This work paves a new avenue to develop accurate reliability model of periphery pFETs, a prerequisite for future device/circuit co-optimization in DRAM peripheral circuits.

IRPS 2022 Main Conference 

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd&gt;Vg Condition for sub-20nm DRAM Technologies

oxide trap

interface trap

hot carrier degradation

dram

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

Please log in to explore this event. You need to log in with the email address you registered with. Access credentials have been sent to your email. 

Please log in to explore this event.

Registration for this conference has now closed. We appreciate your interest and hope to welcome you at a future event. If you’d like to hear about similar upcoming events, please check our website or join our mailing list.

Registration for this conference has now closed.

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Characterization and Modelling of Hot Carrier Degradation in pFETs under Vd>Vg Condition for sub-20nm DRAM Technologies

technical paper

n advanced technology, the effect of self-heating (SH) on hot-carrier degradation (HCD) activation energy (Ea) has been studied by temperature correction under DC stress but frequency dependance of HCD under AC condition is discussed thoroughly. In this study, it is experimentally observed that after considering the influence of SH, device lifetime still increases with shorter stress pulse width. Based on these experimental results, a universal HCD model is proposed which could cover both DC and AC stress waveforms with different pulse width (pstress).

Universal Hot Carrier Degradation Model under DC and AC Stress

We report preliminary results on bias temperature instabilities (BTI) on 28FDSOI MOS transistors from 300K to 4K. Common models describe BTI as a temperature-activated effect, which is suppressed at cryogenic temperature. Our measurements show that some BTI remains even at 4K, underlying another degradation mechanism, and we offer insight into the characteristic temperature and time scales. We show that the back-gate voltage can be used to mitigate BTI degradations. An anomalous signal is observed in small PMOS, which can be caused by trapping from the gate.

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K

Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p- to nFET separation (p-to-n separation), thus enabling further logic cell area scaling without requiring gate length scaling. We report hot-carrier degradation (HCD) simulations of FS FETs and compare this architecture to nanowire (NW) and nanosheet (NS) FETs. HCD is shown to decrease with increasing sheet width in both NS and FS FETs when taking interface state generation into account. Considering that a FS FET can be made wider than an NS FET because of the reduced p-to-n separation, lower HCD for the FS FET is observed. Finally, we make an initial assessment of the impact of oxide defect charging in the FS wall. We confirm decreasing influence of fixed wall charge for increasing sheet widths and estimate that the overall impact of wall charging will stay under control at operating conditions.

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

We extend our framework for hot-carrier degradation (HCD) modeling by covering the impact of self-heating (SH), which has three main aspects: (i) perturbation of carrier transport, (ii) acceleration of the thermal contribution to bond breakage, and (iii) and shortening vibrational lifetime of the bond, i.e. reducing the multiple-carrier mechanism rate. We validate the framework against HCD data acquired in nFinFETs and pNWFETs under various stress conditions, analyze the importance of each of the aforementioned aspects, and explain why in n-channel FETs SH slightly inhibits HCD, while in p-channel devices HCD is accelerated by SH.

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-channel Transistors

A recent progress of NanoBridge (NB) technology is reviewed for embedded nonvolatile field-programmable gate array (FPGA) and memory (NVM) applications. The NB is a kind type of electrochemical resistive-change device using Cu ion migration from Cu interconnects into electrolyte. The NBs are integrated in a standard Cu-BEOL with keeping a PDK and an appropriate ON-conductance is tuned by programming currents depending on the applications. For a routing switch in the FPGA, two NBs are connected in series and each conductance is tuned to ~1mS to transfer signals and realize 78% area reduction compared with a conventional SRAM-FPGA. For the NVM application, that is tuned to ~0.2mS, which has 150oC over 10years retention with 30% change of the conductance, which is potentially applicable for automobile applications.  

NanoBridge Technology: Nonvolatile FPGA and Memory Applications

In advanced DRAM technology, buried-channel-array transistor (BCAT) will generate additional leakage during long-term read/write operations, leading to retention time reduction. In this work, we designed the accelerated aging test in wafer level and proposed a model for the long-term retention time prediction. By adding into conventional retention time simulation flow, the data of retention time at different operation time can be predicted. It was found that the aging can degrade retention time tail around 13% in 10 years. This work is thus helpful to the refresh scheme development considering aging effect.

New Insight into the Aging Induced Retention Time Degradation of Advanced DRAM Technologies

We present a reliable magnetic tunnel junction (MTJ) TDDB model using 40Mb 22FDX® STT-MRAM at sub-PPM failure rate. This model is based on the precise estimation of voltage across MTJ at bit-cell level derived from compact model and design simulations to cover the product level endurance performance from MTJ diameter, resistance-area product, and temperature effects. We discuss the implications of pre/post MTJ switching, circuit variations and write pulse on MRAM endurance. By using design-process-test co-optimization, we show robust MRAM product reliability to meet &gt;1M cycles with solder reflows and path towards achieving &gt;E12 cycles for cache applications.

Extended MTJ TDDB Model, and Improved STT-MRAM Reliability with Reduced Circuit and Process Variabilities

The concept of Abutting source/body and drain/anode junction is studied in detail in high voltage LDMOS-SCR with 2D and 3D TCAD simulations. The SCR turn-on and low current filament formation are strongly influenced by the isolation at the anode and cathode side in LDMOS-SCR. While the anode side isolation impacts the filament-induced failures at low currents, the cathode side isolation has a minor impact. The physical insights are given on the SCR turn-on degradation with abutting and its influence on the filament formation and spreading. The obtained understanding helps to build the ESD robust, self-protected LDMOS-SCRs. 

Effect of Source & Drain Side Abutting on the Low Current Filamentation in LDMOS-SCR Devices

The root causes for the anomalous Pf-tf scaling behavior in the adiabatic regime are identified for a BiCMOS-based ESD protection for the first time. TCAD is used both to understand the turn-on of the integrated architecture with two coupled bipolar transistors under different ESD pulses and to explore the main physical mechanisms leading to the thermal runaway and failure. Simulations clearly show the complex interaction between the conductance modulation and the onset of hot spots in the full volume of the device structure, leading to the identification of critical parameters for the optimization of the proposed ESD cell.

TCAD investigation of Power-to-Failure evaluation for ultrafast events in BJT-based ESD protection cells

In this work we compared AC and DC bias temperature instability (BTI) degradations induced by stressing the channel and Junction-FET regions in 4H polytype n-channel Silicon Carbide (SiC) based power MOSFETs. We observed that the degradation caused by AC BTI stress is dependent on the device technology generation unlike the DC BTI stress degradation, which is found to be independent of technology generation. Also, we found that the AC BTI stress causes more permanent damage to the device due to the creation of interface traps and border traps in contrast to DC BTI where only border traps are responsible for the degradation. 

Premium content

Downloads

Next from IRPS 2022 Main Conference

Universal Hot Carrier Degradation Model under DC and AC Stress

Similar lecture

Towards the Characterization of Full ID-VG Degradation in Transistors for Future Analog Applications