United States

The impact of Program/Erase (P/E) cycling on Cell VT Distribution (CVD) during retention bake in 3-D NAND Charge Trap Flash (CTF) arrays is modeled. Experimental data under Solid Pattern (SP) test is analyzed using Activated Barrier Double Well Thermionic (ABDWT) model. Only two adjustable parameters can model DR loss across various P/E cycles, Bake Temperature (BT), Programming Levels (PL) and CVD levels (sigma). The relative contributions from the underlying physical mechanisms are determined.

IRPS 2024 Main Conference

Modeling of Post-Cycling Retention Bake in 3-D CTF TLC NAND Arrays

abdwt model

data retention

nand flash memory

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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Please register!

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

We have performed high resolution conductance measurements in a wide range of frequency from 1 Hz-10 MHz on thermally oxidized and NO annealed MOS capacitors. We identified the energetic position of fast and slow border traps with respect to EC of SiC and estimated the σc and their location in the oxide. In the final paper, we will provide a comparative analysis of border traps across a range of samples, with distinct annealing treatments.

Exploring the border traps near the SiO2-SiC interface using low frequency conductance measurements

Product reliability, encompassing both manufacturing and operational aspects, is emerging as a crucial aspect of design across iterative chip-package-system design cycles, especially those products anticipated to endure for longer lifetime and possible severe operation environment, necessitate careful consideration of Multiphysics-based reliability enhancements while addressing the interdependencies among different reliability requirements. This paper introduces the innovative EDA solution on Design for Reliability (DFR) workflow with Multiphysics consideration, crossing from IP level, chip, and package/PCB levels. 

Design for Reliability (DFR) Aware EDA Solution for Product Reliability

We report distinct breakdown mechanisms in CVD monolayer MoS2 FET devices for the first time mediated by either voltage or currents in devices. A detailed analysis of the breakdown physics explains the operational effects led shortcomings expected in downscaled devices. Operating short channel TMDs devices would be tricky owing to the dipole moment making it imperative to address the piezoelectric response related drifts in search of reliable performance.

Decoupling Current and Voltage Mediated Breakdown Mechanisms in CVD MoS2 FETs

In this work we develop an ALD grown IGZO channel analyze physical mechanism and reliability governed by channel defects and demonstrate interface-engineered IGZO (IFE-IGZO)-based transistor with high mobility (µ) and superior reliability.

Low-PBTS defect-engineered high-mobility metal-oxide BEOL transistors

A simplified methodology to link CW (Continuous Wave) RF stresses to complex mission profiles is presented in order to compare the lifetimes of different 40nm PDSOI Power Amplifier (PA) cells, versus bias and under different 5G-FR2 modulation profiles. The best lifetime is achieved when using the most complex 5G modulation due to output power/linearity constraints. VT drift correction is also identified as a powerful tool to increase transistor HCI lifetime under PA operation.

A Methodology to address RF aging of 40nm CMOS PA cells under 5G mmW modulation profiles

A robustness assessment has been performed for 77GHz power amplifier. First, a study performed at device level with RF stress illustrates the process capability to support HCI for aggressive mission profile, then secondly a robust setup OLT has been used to carry out 500h stress on several samples. The spread observed on degradation can be explained with Monte Carlo simulation of the complete TX chain. Adequation with ageing model are rather good.

Robustness assessment through 77GHz Operating Life Test of power amplifier for radar application in 28nm FD-SOI CMOS

This study detects recycled ICs by assessing aging-related degradation in intrinsic I/O pad transistors. We do this by: (i) configuring Arm Cortex-M0+ microcontrollers (32 and 72 MHz) to access individual I/O buffer transistors (NMOS/PMOS), (ii) examining NBTI/PBTI degradations in these PMOS and NMOS transistors under AC and DC stress, and (iii) developing an algorithm to distinguish between recycled (with estimated age) and new ICs based on the degradation rate in the NMOS/PMOS under stress.

Validating Supply Chain against Recycled COTS ICs using I/O Pad Transistors: A Zero-Area Intrinsic Odometer Approach

NBTI of IGZO TFTs is studied using diverse devices and conditions. Four main characteristics are observed: V th shift is almost independent of V g_stress, and shows a large activation energy and a steep time kinetic, while the relaxation rate decreases with increasing temperatures. Using TCAD and modelling, these peculiar features can be explained by an oxide-field-dominated hydrogen release at gate side of the gate-dielectric, inducing additional doping and the negative V th shift.

Fundamental understanding of NBTI degradation mechanism in IGZO channel devices

We report on charge capture and emission of Metal-Oxide-Semiconductor AlGaN/AlN/GaN High-Electron Mobility Transistors (MOSHEMT). Defects in HfO2 or AlO result in significant instabilities, with dielectric-dependent emission: band alignment between high-k shallow defect levels and AlGaN conduction band enables full (Al2O3) or partial (HfO2) charge de-trapping. These findings are significant as reliability modes under DC stress also contribute at RF operating conditions.

DC Reliability study of high-k GaN-on-Si MOSHEMTs for mm-Wave Power Amplifiers

Pioneer chip markets, such as data centers or the automotive industry, have a growing demand for dependable and secure chips to sustain power efficiency and long-term performance. The inevitable degradation of chip reliability caused by the two major aging mechanisms, BTI and HCD, may cause critical chip performance degradation. In this paper, we present our latest on-chip odometer technology, employed to accurately quantify in-field Si degradation using our two new designs of RO-based odometers.

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Exploring the border traps near the SiO2-SiC interface using low frequency conductance measurements

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