United States

Temperature-accelerated methods are generally used for lifetime evaluations in Flash memories products. However, in this article, an anomalous negative temperature dependence of erase-state threshold voltage (Vt) retention gain in post program/erase (P/E) cycled 3-D NAND Flash memories is reported for the first time, which would lead to a methodological problem of the conventional temperature-accelerated life-test approach. Based on our experiment results, the phenomenon is realized due to the combination of two physical mechanisms. Erase Vt gain at lower temperatures is mainly attributed to silicon nitride (SiN) trapped hole vertical loss via oxide trapped charges created by high P/E cycling stress. At higher bake temperatures, the influence of oxide trapped electron detrapping process is enhanced and Vt gain is therefore reduced. By performing a special experiment, the activation energy of the trapped electron detrapping process is extracted. 

IRPS 2022 Main Conference 

An Abnormal Negative Temperature Dependence of Erase-state Vt Retention Shift in 3-D NAND Flash Memories

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

poster

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Gate oxide Time Dependent Dielectric Breakdown (TDDB) continues to be a major reliability concern for advanced CMOS nodes with increasing quality requirement standard such as for automotive industry. Therefore, significant effort has been made to accurately model gate oxide TDDB. We propose here a modelling approach to account for our recent results showing significant increase of TDDB with frequency.  

Frequency dependant gate oxide TDDB model

We report on the gate oxide reliability of n-type LDMOS which is integrated in a 90nm BiCMOS technology and is optimized to offer a robust off-state TDDB reliability performance. In contrast to previous published results, we demonstrate that off-state TDDB lifetimes show very weak dependence on the applied drain bias, Vd, thanks to the carefully optimized NWell drift region that effectively shields the channel from the deleterious high electric fields associated with high Vd operation and significantly reduces the vertical electric field across the gate oxide as shown by TCAD simulation results. TDDB lifetimes are then mainly modulated by the gate voltage and are found to be comparable to the lifetimes obtained under inversion and accumulation modes, hence enabling a reliable operation under high Vdg bias levels. 

Robust Off-State TDDB Reliability of n-LDMOS

We propose a geometric statistical model to describe stress-induced leakage current (SILC) as a function of trap density (Dot). We demonstrate how soft breakdown measured on smaller devices is controlled by a 2 traps percolation path and how its voltage dependence coincides with the 1 to 2 traps transition of SILC measured on larger devices. Finally, assuming the high-k as the breaking layer, we convert the 1-trap leakage current into Dot.

Combining SILC and BD statistics for low-voltage lifetime projection in HK/MG stacks

Gate oxide reliability face a big challenge in high temperature automotive application (auto-grade 0). In this paper, we fully discuss the physical mechanism of oxide trap interaction and point out the oxide reliability weakness. It is found the unexpected TDDB behavior at high temperature, include serious SBD, the relationship of voltage acceleration change, and non-linear temperature effect. In addition, the AC/DC effect found more obvious recovery effect. Finally, for mass production, we also import the confidence level usage to give a reasonable lifetime margin for mass production.

A Realistic Modeling Approach To Explain the Physical Mechanism of TDDB For Automotive Grade-Zero Applications

We propose a novel method of predicting electron and hole lateral diffusion in a charge trapping layer of 3D TLC NAND by which we can estimate the long-term lateral migration (LM) behavior in a short time. By monitoring the threshold voltage change (△Vth) of the select cell under various bias and temperature conditions, we observe that electron and hole lateral diffusivity matches well with the Poole-Frenkel (PF) model. The lateral diffusivity is extracted by measuring △Vth when the electrons and holes of neighboring cells reach the selected cell. 

Electric Field Impact on Lateral Charge Diffusivity in Charge Trapping 3D NAND Flash Memory

We simulate saturation drain current changes during hot-carrier degradation (HCD) in dynamically-doped (D2) and planar CMOS FETs of a similar architecture. To achieve this, we use our HCD model validated against experimental data over a broad class of transistors. These simulations show that at Vgs ≤ 0.9V (covering the operating regime) D2 FETs have superior reliability, while at Vgs ≥ 1.0V the CMOSFET begins to be more reliable. Under these stress voltages, HCD is governed by the multiple-carrier process of bond dissociation controlled by the carrier concentration (rather than energy), which has different Vgs dependences in D2 and CMOS FETs.

On Superior Hot Carrier Robustness of Dynamically-Doped Field-Effect-Transistors

We present a detailed analysis of Off-state Time Dependent Dielectric Breakdown (TDDB) under non-uniform field performed in MOSFET devices from 28nm FDSOI, 65nm SOI to 130nm nodes. Oxide breakdown in thin gate oxide is characterized under DC stress with different gate-length LG and as function of drain voltage VDS and temperature. We show that the leakage current is a better monitor for TDDB dependence under Off-mode stress whereas a new modeling is proposed. It is found that Weibull slopes β are higher in PFET due large amount of injected hot electrons than in NFET when hot holes are involved.

New Modelling Off-state TDDB for 130nm to 28nm CMOS nodes

Be closer to real product operation, DC TDDB stress convert to AC TDDB could be one choice to wrestle with advanced node shrink limitation. The physical explanation of AC TDDB improvement is successfully interpreted through the analysis of oxide trap generation with HK/IL gate stack in advanced node FinFET technology using SILC spectrum methodology. It is found that AC TDDB improvement is due to more charge de-trap. NMOS show less shallow and deep electron trap generation on HK and PMOS show less hole trap generation on IL during AC waveform transition.

AC TDDB Analysis for HK/IL Gate Stack Breakdown and Frequency-dependent Oxygen Vacancy Trap Generation in Advanced node FinFET Devices by SILC Spectrum Methodology

We have investigated and report here for the first time time-dependent dielectric breakdown (TDDB) in 45-nm RFSOI n-channel floating body MOSFETs at cryogenic temperatures. DC constant voltage stress is applied at the gate while the substrate chuck temperature is varied from 300K down to 10K. While t63 decreases with increasing temperature, shape parameter β shows an inverted U-shaped behaviour which is explained using the bandgap model. Three levels of activation energy are seen for high, low and deep low temperatures where the activation energy decreases from high to deep low temperatures. The observed behaviour is further explained using the bandgap as per the percolation theory.

Deep Cryogenic Temperature TDDB in 45-nm PDSOI N-channel FETs for Quantum Computing Applications

The sub-THz spectrum between 100GHz and 300GHz is of great interest for achieving next generation 6G cellular network goals of ultra-high data rate, ultra-low latency and high sensing precision. Carrier frequencies &gt;100GHz create significant challenges, including higher losses, lower semiconductor device performance, and a smaller per element physical area that constrains circuit size, integration, power and thermal management. Semiconductor technologies with transistor performance &gt;500GHz are needed for improved efficiency, gain, noise and area at the front end of the 6G phased array radio. Advances in SiGe BiCMOS have the potential to increase silicon transistor performance while leveraging the cost and scale of mature high-volume silicon manufacturing for 6G sub-THz. Compound semiconductor technologies such as InP and GaN have the best front end performance at sub-THz. Advances in heterogeneous and monolithic integration with silicon are needed to address the cost and scale concerns of high frequency InP and GaN.  A comprehensive approach to reliability is essential in order to extract maximum performance without sacrificing reliability.

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Frequency dependant gate oxide TDDB model

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