United States

Field-effect transistors (FETs) based on two-dimensional (2D) materials hold the promise to allow for ultimately scaled channel thicknesses of single monolayers. Due to their ultimately small thicknesses, the gate control is enhanced while sizable mobilities in the 2D semiconductors are maintained. Thus, in recent years considerable research efforts have focused on 2D FETs and explored various 2D semiconductors and their properties. However, the key challenge of finding suitable gate insulators for 2D FETs has yet received little attention. In this paper, criteria are formulated for identifying suitable gate insulators for reliable 2D FETs. The criteria are grouped into three main categories, these are scaling requirements, reduction of insulator-related charge traps, and technological requirements for the insulator deposition. In addition, possible candidates for gate insulators for 2D FETs are evaluated with respect to the formulated criteria, and important research questions for future investigations are identified.

IRPS 2022 Main Conference 

Finding Suitable Gate Insulators for Reliable 2D FETs

semiconductor device reliability

high-k gate dielectrics

reliability engineering

nanoelectronics

2d materials

**IRPS 2024 Tutorials were held in Dallas, Texas from April 14 to 15, 2024. The IRPS Reliability Year in Review (YIR) session consisted of three presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It was a nice augmentation to the tutorials sessions immediately preceding and attendees were able to obtain keen reliability insights in short amount of time.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**
Please save the zip file locally and click the "start.pdf" to view the file. 

**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Tutorials and YIR

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

technical paper

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

This paper will discuss how deep data analytics based on Universal Chip Telemetry™ (UCT) offers a new approach to lifecycle health and performance monitoring in advanced electronics. By combining on-chip monitoring with machine learning inference in the cloud and edge, production quality is improved through advanced latent defect detection, while lifetime reliability is increased through degradation monitoring and predictive fault detection.

Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

Simulations based on first-principle modeling of material structural features determining electrical properties of a CNT memory cell allow to identify a range of operation conditions delivering desirable device characteristics. This approach designates the path for optimization of the CNT memory device structure to meet the performance requirements.   

Combining measurements and modeling/simulations analysis to assess carbon nanotube memory cell characteristics

Contacts stability versus thermal budget is a major concern in 3D sequential integration. We experimentally investigate the thermal stability of n-type contacts on Si and p-type contacts on SiGe in terms of specific contact resistivity (ρc). An improved ρcn performance featuring lower magnitude and better thermal stability has been demonstrated for Ti silicide contacts on n+-Si with Ge pre-amorphization implantation (PAI). For p-type contacts, it is found that Ni has lost its high work function advantage on p++-SiGe and Ti germanosilicide contacts show ρcp outperformance. CMOS contact scheme based on single Ti instead of dual Ti and Ni has hence been evidenced to be more suitable for 3D sequential integration.

Investigation on Contacts Thermal Stability for 3D Sequential Integration

Silicon oxynitride (SiON) is widely applied as ultra-thin gate oxide for LNA, with its better resistance to high electric field stress and higher dielectric constant than conventional SiO2. However, the gate leakage still inevitably increases to a non-negligible level as gate oxide been thinned down till &lt;15A.  In this paper, rapid thermal process (RTP) was employed to fabricate a series of SiON gate oxide film. It was found that pre-Nitridation O2 treatment at lower temperature effectively optimize the N-dose profile in SiON and suppresses the gate leakage without significant impact on LNA DC/RF performance. .

Pre-O2 treatment for LNA gate oxide leakage improvement

We propose an electrical detection method for peripheral circuit (PERI) ‘open’ random defects. This brand new screening methodology detects only PERI defects by independently controlling the supply voltage (VDD) of each circuitry array at low temperature. The proposed method is confirmed based on experimental, simulation, and physical analysis results. Compared with conventional function test items, our proposed method shows &gt;50% error reduction.

Novel Electrical Detection Method for Random Defects on Peripheral Circuits in NAND Flash Memory

On-chip degradation monitoring enables reliable recycling of chips in the context of circular economy by assessing their degradation and thereby inferring their remaining lifetime. Implementations of such monitors have already been presented typically relying on ring-oscillator-based circuits to evaluate degradation undergone by ICs. However, these approaches are not able to distinguish between the physical degradation and the time since fabrication and they can be tampered with high temperature annealing. In this work we present a new concept of degradation monitor circuit, which can obtain the age of the chip and detect if the chip has undergone tampering through high-temperature annealing.

A Ring-Oscillator-based Degradation Monitor Concept with Tamper Detection Capability

For the design of reliable ICs the application of accurate transistor aging models is indispensable. However, especially for modern deeply-scaled technologies modeling NBTI induced aging poses significant challenges as transistors can not be characterized individually but need to be described as a statistical ensemble. We make use of a dedicated array structure enabling the collection of a large data-set at reasonable experimental time. Note that by using an extensive data-set the statistical confidence can be maximized. We present a modeling approach based on physical considerations to describe the aging of SRAM-sized transistors under consideration of statistical effects. Our approach applies a modified defect-centric model under consideration of RTN to describe the time-dependent Vth distribution. Furthermore, we introduce a simple method to extract parameters describing the distribution. Additionally, we show that our approach provides great flexibility regarding stress conditions as well as scalability to different transistor dimensions, which makes it ideal for applications such as circuit simulation.

Efficient Evaluation of the Time-Dependent Threshold Voltage Distribution Due to NBTI Stress Using Transistor Arrays

The block size of flash memory chips has increased significantly with the introduction of 3D NAND technology, causing “big-block” management issues in storage systems. In this paper, we characterize endurance of individual pages in a block and show that pages in the bottom and top layers exhibit lower endurance than pages in the middle layers. This variation in endurance among pages can cause severe underutilization of big memory blocks. We find that erase threshold voltage () variation between the layers is the root cause for the observed endurance variation. 

Layer-to-Layer Endurance Variation of 3D NAND

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

DC & RF Reliability Assessment of 5G/mmW capable GaN HEMT Process

Fault injections and attacks on an integrated circuit (IC) chip using a variety of physical measures are reviewed. Laser fault injection (LFI) is highlighted for the essential vulnerability on the backside of an IC chip in flip-chip packaging. On-chip voltage waveform monitoring characterizes the voltage peaks induced by LFI and establishes the detection scheme against LFI attacks. The backside buried metal (BBM) technique is deployed by preventive measures for shielding from laser exposure, for avoidance and also waring of invasive laser attacks. The alleviation of backside LFI is proven by Si experiments with on-chip waveform monitoring.

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Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

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