United States

We extend our framework for hot-carrier degradation (HCD) modeling by covering the impact of self-heating (SH), which has three main aspects: (i) perturbation of carrier transport, (ii) acceleration of the thermal contribution to bond breakage, and (iii) and shortening vibrational lifetime of the bond, i.e. reducing the multiple-carrier mechanism rate. We validate the framework against HCD data acquired in nFinFETs and pNWFETs under various stress conditions, analyze the importance of each of the aforementioned aspects, and explain why in n-channel FETs SH slightly inhibits HCD, while in p-channel devices HCD is accelerated by SH.

IRPS 2022 Main Conference 

Understanding and Modeling Opposite Impacts of Self-Heating on Hot-Carrier Degradation in n- and p-channel Transistors

nanowire fet

lattice heat flow equation

carrier transport

hot-carrier degradation

self-heating

finfet

modeling

**IRPS 2024 Tutorials were held in Dallas, Texas from April 14 to 15, 2024. The IRPS Reliability Year in Review (YIR) session consisted of three presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It was a nice augmentation to the tutorials sessions immediately preceding and attendees were able to obtain keen reliability insights in short amount of time.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**
Please save the zip file locally and click the "start.pdf" to view the file. 

**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Tutorials and YIR

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

technical paper

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

Benefitting from forksheet device co-integration with nanosheets, we evaluate the reliability concerns that come along the use of the SiN-based dielectric wall. This wall could act as a “sponge” for non-equilibrium charges during hot-carrier stress, or absorb charges resulting from the horizontal field between n- and p-type devices. In-depth analysis showed no significant charge trapping phenomena were caused by the presence of the SiN wall. Both BTI and—after accounting for processing imperfections—HCI reliability were found to be comparable. We conclude the SiN dielectric wall does not constitute an additional reliability concern for the novel FSH architecture.

Evaluating Forksheet FET reliability concerns by experimental comparison with co-integrated Nanosheets

Two key mechanisms (i) trapping induced Parasitic Drain Series Resistance (PDSRI) and (ii) interface state generation Nit are both identified within non-conducting hot carrier injection (NCHCI). During NCHCI stress, the drain current degradation due to PDSRI is observed at the first time readout as a sudden shift and is followed by conventional (relatively lower) monotonically increasing shift due to interface state generation. The convolution of these two phenomena, complicates the extraction of their unique model parameters and lifetime extrapolation. Characterization methods to isolate each is demonstrated. Their separate dependencies on gate length, drain voltage, and temperature are 










studied and modeled. Using TCAD simulations, the differences in 
the damage rate and location due to PDSRI and Nit are studied. By 
understanding the E-field distribution, the charge trapping in the 
side wall spacer region is found to be the key contributor to PDSRI 
behavior under NCHCI conditions.

Parasitic Drain Series Resistance Effects on Non-Conducting Hot Carrier Reliability

Significant improvement of channel mobility in SiC MOSFETs with high reliability and deep understanding of bipolar degradation in SiC are presented. By excluding oxidation of SiC while adopting H2 etching prior to oxide formation and interface nitridation, a low interface state density of 6×1010 cm-2eV-1near the conduction band edge was achieved in SiC(0001) MOS structures, which resulted in more than two-fold improvement of channel mobility. A physics-based model for stacking fault expansion upon excess carrier injection is proposed. The critical excess carrier density for stacking fault expansion was estimated to be (4–6)×1014 cm-3 at 300 K. A design guideline of a “recombination-enhancement layer”, which prevents hole injection into the underlying substrate, is described. 

Optical Emission Correlated to Bias Temperature Instability in SiC MOSFETs

We investigate and model the threshold voltage instabilities of 4H-SiC power MOSFETs at room and cryogenic temperatures, based on wide time range (from µs to ks) PBTI analysis. We show that for T &gt; 200 K a stretched (log-like) de-trapping transient dominates the recovery kinetics, while at lower temperatures (down to 80 K) a fast exponential component is also visible. The charge de-trapping process is modeled as a distribution of traps spread over the midgap, that causes the threshold instability. Results indicate: i) one narrow gaussian energy distribution at the interface, visible at low temperature, which explains the exponential transient behavior for T &lt; 200 K; ii) a broader distribution deeper in energy, that is considered to take into account the logarithmic de-trapping kinetics at higher temperatures and the threshold static shift with temperature. The proposed modeling framework can accurately reproduce the experimental results.

Analysis and Modeling of Vth Shift in 4H-SiC MOSFETs at Room and Cryogenic-Temperature

We investigate the mechanism governing threshold voltage (VTH) hysteresis in packaged SiC MOSFETs. A double-ramp measurement method was employed for this scope, being able to accurately evaluate the time-dependent recovery of the positive VTH shift induced by the sweep-up of the gate voltage. Particularly, we studied the effect of the (i) gate driving voltage (VGH), (ii) recovery time (TOFF) and (iii) temperature (T) on the VTH hysteresis. No appreciable differences were observed among data collected at different VGH, whereas a recovery speed-up was observed at higher T values. Temperature dependent measurement of VTH recovery yielded a 0.3 eV activation energy, that has been associated to SiC/SiO2 interface traps located ~0.3 eV below the SiC conduction band.

Identification of Interface States responsible for VTH Hysteresis in packaged SiC MOSFETs

At the 7-nm bulk FinFET node, latchup effects are seen as limited current increases. In this work, 7-nm node latchup susceptibility is evaluated for terrestrial and space environments as a function of supply voltage, temperature, and particle LET. Holding voltage for latchups is strongly dependent on temperature and was observed to be within 100 mV of nominal supply voltage, therefore latchup can be sustained at elevated supply voltages. Latchup SE cross-section increases with increasing particle LET, increasing supply voltage, and increasing temperature. 

Latchup Vulnerability at the 7-nm FinFET Node

This work presents a high-voltage-tolerant (HVT) supply clamp for ESD protection, in which the current drive of the clamp during an ESD event is maximized without compromising reliability during normal operation. Similar to prior HVT clamps, ESD current shunting is provided by 3 cascoded NFETs; however, the trigger circuit is improved. The design is implemented in a 45-nm SOI CMOS technology and the clamp devices are sized for a 2-kV HBM protection level. As evidenced by TLP and VFTLP measurements, the new clamp offers 50% reduction of on-resistance and 0.6 V lower turn-on voltage, relative to the prior art.

A High Voltage Tolerant Supply Clamp for ESD Protection in a 45-nm SOI Technology

Forksheet (FS) FETs are a novel transistor architecture consisting of vertically stacked nFET and pFET sheets at opposite sides of a dielectric wall. The wall allows reducing the p- to nFET separation (p-to-n separation), thus enabling further logic cell area scaling without requiring gate length scaling. We report hot-carrier degradation (HCD) simulations of FS FETs and compare this architecture to nanowire (NW) and nanosheet (NS) FETs. HCD is shown to decrease with increasing sheet width in both NS and FS FETs when taking interface state generation into account. Considering that a FS FET can be made wider than an NS FET because of the reduced p-to-n separation, lower HCD for the FS FET is observed. Finally, we make an initial assessment of the impact of oxide defect charging in the FS wall. We confirm decreasing influence of fixed wall charge for increasing sheet widths and estimate that the overall impact of wall charging will stay under control at operating conditions.

Simulation Comparison of Hot-Carrier Degradation in Nanowire, Nanosheet and Forksheet FETs

With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime.

Impact of Transistor Reliability on Memories and Memory Periphery Circuitry

This paper presents a new compact model for ESD diodes named Advance SPICE Model for ESD diodes (ASM-ESD). In addition to the current-voltage (I-V) and the capacitance-voltage (C-V) behaviors of the diode under normal operating conditions, ASM-ESD has capabilities to model a plethora of important effects critical for the ESD applications. Model features include the ability to capture the overshoot effects, ambient temperature effects, self-heating effect, post reverse breakdown resistance, parasitic BJT gain, transient behavior of BJT gain and reverse recovery effects in ESD diodes. ASM-ESD model formulations have a physical basis leading to an intuitive extraction flow. Model comparisons with measurements for DC I-V, C-V, and TLP with pulse widths ranging from 200 ns to 1.2 ns are presented. These results demonstrate model accuracy for a full range of ESD event scenarios. 

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Evaluating Forksheet FET reliability concerns by experimental comparison with co-integrated Nanosheets

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