United States

Benefitting from forksheet device co-integration with nanosheets, we evaluate the reliability concerns that come along the use of the SiN-based dielectric wall. This wall could act as a “sponge” for non-equilibrium charges during hot-carrier stress, or absorb charges resulting from the horizontal field between n- and p-type devices. In-depth analysis showed no significant charge trapping phenomena were caused by the presence of the SiN wall. Both BTI and—after accounting for processing imperfections—HCI reliability were found to be comparable. We conclude the SiN dielectric wall does not constitute an additional reliability concern for the novel FSH architecture.

IRPS 2022 Main Conference 

Evaluating Forksheet FET reliability concerns by experimental comparison with co-integrated Nanosheets

forksheet

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

Design of reliable and high-performance RF power amplifiers in CMOS technologies is becoming more challenging due to the increasing reliability issues as we approach the scaling limit. To provide insight on hot-carrier injection (HCI) degradation at RF frequencies, this paper presents a comprehensive analysis to study this effect on different PA architectures based on their mission profile with a quasi-static approach. Sensitivity analysis on power amplifier RF performance is also discussed to offer a better understanding on the importance of accurate device and aging behavior modeling. 

Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

RF reliability of 40-nm PDSOI nFET power amplifier (PA) cell at 26.5GHz is investigated. DC and RF stresses are applied in conducting and non-conducting hot carrier stress mode to study the PA cell RF and DC degradation behaviour. The relationship between DC and large-signal RF performance under various RF stress conditions is investigated using DC and RF metrics. The degradation rate depends on RF power and terminal voltages, where ~8X lower degradation is observed at low VGS. During RF stress, the DC performance degradation rate is higher in the linear operating region than the saturation region. The impact of RF stress is amplified in the presence of DC stress, accelerating the degradation of PA cells. For different VGS under RF stress conditions, the lifetime of the PA cell is calculated and compared.

RF Reliability of CMOS-Based Power Amplifier Cell for 5G mmWave Applications

Power Amplifier (PA) is a key component for embedded RF/mmWave on advanced CMOS technologies on the way to replace the III/V technologies. PA reliability has been a long-standing blocker for those applications. In this paper, a novel methodology is introduced based on an automated waveform analysis tool. Simulation aging results are compared with experimental silicon validation stress for a 28GHz high gain RF Power Amplifier (PA) and confirmed. Waveform analysis tool enables a deeper understanding of both continuous waveform (CW) with constant load and ruggedness test, as well as a new perspective about RF/mmWave circuit aging. 

22FDX™ 5G 28GHz 20dBm Power Amplifier Constant Load and VSWR accelerated aging reliability

RF High Temperature Operating Life (HTOL) of  5G mmWave beamformer chip is evaluated at 28GHz under worst case operating life conditions. Each packaged chip with 8 channel Power Amplifier used for generating omnidirectional beam was evaluated for &gt;= 120hrs at 0.1%CCDF under accelerated Psat RF stress at Tj ~ 85C. Excellent initial RF metrics were observed for all ~32 samples measured. Overall Pout and gain degrades by &lt;0.5dB while DC current degrades &lt;10% meeting the 10yr product life criteria demonstrating excellent RF HTOL processed using GF 45RFSOI technology. Excellent aging model to hardware correlation was also observed showing excellent predictability.

Excellent RF Product HTOL reliability of 5G mmWave beamformer chip fabricated using GF 45RFSOI technologies

The electrical reliability of 1 μm pitch wafer-to-wafer(W2W) Cu/SiCN hybrid bonding interface is evaluated.Breakdown voltage distributions of the W2W hybrid stack wereacquired using the controlled-IV method. Assuming a power lawmodel, extrapolation towards use conditions confirm a lifetimeabove 10 years, with a power law exponent above 10 fortemperatures under 175 C. The conduction mechanism along theCu/SiCN hybrid bonding interface is found to be Poole-Frenkelemission with energy barrier equals 0.95 eV. Mobile copper couldonly be observed at temperatures above 200 C and for fieldsabove 1.5 MV/cm, confirming the good robustness against copperdrift for this bonding interface.

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism

Hybrid Bonding (HB) is progressing as the major solution for 3D integrated-circuit with pitch reduction becoming the key. Reliability needs to be studied with HB pitch reduction for possible evaluation of new failure mechanisms and modes. In this paper, we developed a new methodology to study Time-Dependent Dielectric Breakdown (TDDB) at HB level that accounts wafer-to-wafer (W2W) overlay variations. Application of this method to a 1.44 µm-pitch 3D stacked test vehicle demonstrates its accuracy. TDDB at Cu/SiO2 HB interface follows the 1/E model at low electric fields for all studied temperature suggesting that the role of Cu in breakdown is negligible. The acceleration parameter and the activation energy dependence on the electric fields are studied. The cuprous oxide layer which may act as a barrier to Cu diffusion previously highlighted at the Cu/SiO2 HB interface does not exist for Cu/SiN interfaces as evidenced by EELS study. This might explain the difference in the TDDB acceleration models between HB level and BEoL ones. 



New Method to Perform TDDB Tests for Hybrid Bonding Interconnects

Aggressive technology scaling coupled with an insatiable need for high-performance microprocessors has led to a significant increase in power dissipation in integrated circuits. This has, in turn, led to an increase of within-die thermal gradients. In this paper, we present a novel approach of assessing the impact of spatial and temporal hotspots on the chip-package interaction (CPI) reliability of microprocessors using an on-die ring oscillator (ROSC) based heater. The ROSC design enables the generation of temperature hotspots with power densities exceeding 3000 W/cm2, allowing assessment of its impact on CPI reliability. The fast response of the ROSC heater enables high-frequency thermal cycling, which can be used to assess CPI reliability for cycle counts of the order of a few million. This methodology can be used to mimic the thermal cycling behavior of microprocessors under realistic workloads and can be used as a tool to improve confidence in thermo-mechanical reliability.

A Novel Approach for Assessing Impact of Temperature Hot-Spots on Chip-Package Interaction Reliability

It is well known device parameters like mobility can be significantly affected by the stress induced by TSV in 3DIC. For the sake of long-term application, the impact of TSV stress on device reliability also requires attention. This study presents detailed characterization and analysis of TDDB performance of FinFET devices placed in the neighborhood of TSV. It is found the TDDB lifetime of the devices stressed under substrate injection mode could be seriously worsened by neighboring TSV, while that of the devices stressed under gate injection mode only shows moderate degradation. It is proposed the defect generation in high-K layer, which controls the TDDB performance under the former stress mode, may be more sensitive to mechanical stress than that nearby IL/Si interface which dominates under the latter mode. It can be ascribed to considerable charge trappings in HK during stress, which could significantly lower the stiffness of Hf-O and thus reduce the energy required for defect generation under the impact of the stress induced by TSV. It also shows the impact of TSV on TDDB has no considerable orientation dependence. The study suggests careful characterization of the reliability, other than the performance, of the devices nearby TSV with specifically designed test structure, is essential for evaluation of TSV-enabled 3DIC. 

Impact of TSV on TDDB Performance of Neighboring FinFET with HK/IL Gate Stacking

A stress and measurement sequence is presented for the detection of plasma induced damage (PID) instabilities during process reliability monitoring on product wafers of integrated circuit mass production (fWLR Monitoring). The significance of a lifetime estimation from reliability data of antenna test structures is demonstrated with respect to automotive quality requirements in contrary to commonly used approaches in industry. It is shown that a comprehensive approach is necessary starting with appropriate test structures, the PID process qualification and the definition of sophisticated design rules. A short constant current stress as revealing reliability stress for hidden damage fulfills the demands and is discussed in detail including a literature review.

Plasma processing induced charging damage (PID) assessment with appropriate fWLR stress methods ensuring expected MOS reliability and lifetimes for automotive products

With HPC devices continue to scale up for higher power and higher power density, thermal dissipation management for IC packages are becoming an important issue. This paper presents the thermal solution evolution at package level and system level, that drives towards more advanced package TIM1 solution and liquid or immersion cooling solution. Thermal-aware device floorplan, package thermal solution and advanced system cooling solution are critical to enable HPC application.

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Comprehensive Analysis of RF Hot-Carrier Reliability Sensitivity and Design Explorations for 28GHz Power Amplifier Applications

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