United States

A low conduction resistance 1200 V/ 4 mΩ SiC power module is fabricated and characterized for its thermal performance. The design and fabrication of the power module is presented. The parasitic resistance distribution from the module prototype is measured and shows that it is critical to minimize the source bond wire and contact resistance for such low on-state resistance module. The steady-state thermal tests are performed, and the temperature distribution of the fabricated module is measured and validated. A FEA model of the SiC module is built and validated by the steady-state thermal tests. Then the transient thermal performance or surge current capacity is studied. It shows that at least 4 bond wires are required for each SiC die such that the module package will not limit the surge current capacity of SiC chips.

IEEE WiPDA 2021

Development and Thermal Characterization of a Low Resistance SiC Module

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

[![](https://assets.underline.io/uploads/markdown_image/1/image/c8e1b0a2881d3bb0a75ece4761f43c9f.png)](https://drive.google.com/drive/folders/1GWEFLzH6K4aUBaJiBFJDw4x9sKLTl6-g?usp=sharing)


This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

poster

6.5 kV-rated 4H-SiC MOSFETs have been successfully fabricated and demonstrated on 60 µm-thick, 1.2×1015 cm-3 doped N-type epi-layer on 6-inch, 4H-SiC N+ substrates. Devices were fabricated at the 6-inch SiC foundry, X-FAB, TX, USA. Active and edge termination areas of high voltage (>3.3 kV) SiC devices require critical design consideration due to implant straggles from the low background doping concentration. Despite the fabrication and design challenges, we have demonstrated Ron,sp of 47 mΩ-cm2 with a breakdown voltage of 7.9 kV with a very low leakage current using ring-based edge termination structure. Devices were then diced and packaged in a SUNY Poly’s custom-made package to evaluate short circuit capabilities. Short circuit withstand time of 6.2 µs was recorded from the nominal device, along with 7 µs and 13 µs from the device with narrower JFET width and wider channel length, respectively.

Critical Design Considerations for Static and Dynamic Performances on 6.5 kV 4H-SiC MOSFETs Fabricated in a 6-inch SiC Foundry

This talk discusses the dynamic characterization of a 3.3 kV SiC-based reverse voltage blocking switch for three different switch configurations used for the current source inverter (CSI). The static characterization of the devices is done for the latest generation 3.3 kV SiC MOSFET and diode. Based on these results, a preferred current switch is suggested for a medium voltage CSI.

Performance Evaluation of 3.3 kV SiC MOSFET and Schottky Diode for Medium Voltage Current Source Inverter Application

For efficient converter design, modeling of switching components must be both accurate and fast. A variety of simulation models
for SiC Power MOSFETs has been developed. To achieve adequate accuracy, models are adjusted to experimental data by applying fitting methods. However, proposed universal fitting methods result in high-dimensional optimization problems. Their computational inefficiency leads to either long run times or low accuracy. This paper proposes a new universal parameter fitting method that is at least twice as fast and yields a more accurate outcome than presented methods under comparable conditions. It effectively reduces the dimensionality of the parameter fitting optimization problem by sensitivity-based reduction of optimization parameters.
Thereby, it optimizes both model adjustment speed and accuracy, which are critical factors for an efficient converter design process. The method does not compromise flexibility as it is universally applicable to any SPICE model and can meet any model architecture preference.

Smart Universal Parameter Fitting Method for Modeling Static SiC Power MOSFET Behavior

This paper presents a method that extracts junction temperature of SiC MOSFETs by measuring a unique turn-on delay. In preceding work, the turn-on delay was identified as a particularly promising temperature-sensitive electrical parameter for SiC MOSFETs. The reasons for this are its simple calibration, its insensitivity to the device current, its linear temperature dependency as well as the particular behavior of the charge carrier mobility of SiC. However, state-of-the-art extraction circuits for turn-on delay only work with a limited time resolution. Thus, they can only be applied to slowly switched SiC MOSFETs. This work proposes a circuit for turn-on delay extraction with a time-to-digital converter that allows the time resolution to be significantly increased. Thereby, the circuitry allows utilizing turn-on delay as an effective temperature-sensitive electrical parameter for junction temperature extraction of SiC MOSFET operated with fast switching transients. The feasibility of the approach is experimentally validated in this work with a developed extraction circuit using a SiC MOSFET power module as a device under test.

Online Junction-Temperature Extraction Method for SiC MOSFETs Utilizing Turn-on Delay

In this paper, a comprehensive comparative analysis is performed on the short circuit (SC) withstand time and failure modes between a 650 V SiC Planar MOSFET, a 650 V SiC Trench MOSFET and a 650 V SiC Cascode JFET. The short circuit tests have been performed at a DC link voltage of 400 V with gate turn-OFF voltages at 0 V and -5 V. The results show that the SiC Cascode JFET failed in a source-to-drain short circuit with the gate still capable of blocking voltage while the SiC Planar and Trench MOSFETs failed with the Gate-Source (VGS) terminal short circuited and Drain-Source (VDS) terminals still capable of blocking voltage. Furthermore, short circuit withstand times measured on the SiC Planar and Trench MOSFETs showed an increase (20% for the Planar MOSFET and 9% for the Trench MOSFET) when the device gate voltages were turned-OFF with -5V compared to 0V. This was due to the increased inductance of the negative voltage gate driver reducing the peak short circuit current. In the case of the SiC Cascode JFET, there was no dependence of the short-circuit withstand time on the VGS turn-OFF voltage.

Comparison of Short Circuit Failure Modes in SiC Planar MOSFETs, SiC Trench MOSFETs and SiC Cascode JFETs

With unrivalled better technology-specific figure-of-merits SiC MOSFETs and GaN HEMTs have started to conquer high power applications such as Mobile phone chargers, On-board chargers and Motor drives replacing IGBTs or Superjunction devices. Driven by ever higher demands on power density and efficiency and new trends such as bidirectional power flow for vehicle-to-x applications, wide bandgap power devices have turned into a focal point of design activities. In all of these applications a simple replacement of IGBTs or Superjunction devices by wide bandgap devices may bring already some benefits. The full potential of wide bandgap devices, however, will only be reached when being combined with perfectly matching topologies and control. In motor drives e.g. replacing the IGBTs of a B6 bridge with SiC MOSFETs may result in better efficiency in light load and urban drive cycles. However, switching speed limitations down to around 5V/ns to avoid e.g. partial discharge in the insulation of the motor windings or reflections in long cables, will prevent to increase switching frequencies substantially. In contrast, changing the topology from a voltage source inverter to a current source inverter, which creates a continuous voltage on the machine, opens up a completely new optimization range both for the electric machine and its inverter. Similarly, a transition from modular single phase power stages into true 3-phase active frontends using synergetic control options enables much higher power density for on-board chargers. The presentation will start with a few key characteristics of the involved technologies and their perspective and will highlight system advantages of wide bandgap power devices in a few selected key applications such as Onboard chargers and Motor drive.

On the benefits of SiC and GaN in high power applications

Integrated circuits made using GaN-on-Si substrates have been in production for over seven years. During that time, GaN-based ICs have evolved from pure discrete devices to monolithic half-bridge devices and then onto power FETs that included their own monolithically integrated driver, and more recently, to fully monolithic power stages including power FETs, drivers, level shifting circuits, logic, and protection. In this talk we will look at the roadmap of GaN-on-Si integration and show how the role of discrete transistors is destined to diminish to near-zero in the next few years.

Gallium Nitride Integration and the End of Discretes

GaN power HEMTs are known to offer high switching speed, low on-resistance and much better FOM when compared to their silicon counterparts. However, the ability to operate with high power density in a smaller form factor presents new challenges for reliable and robust operation. Traditional gate driver designs for silicon-based power devices are catered to lower frequencies with large tolerance on the gate voltage swing. They do not adequately address some of the reliability issues that are unique to GaN power transistors. This talk will provide a quick review on the gate driving requirements and limitations for GaN power HEMTs. This is followed by a survey of novel smart gate driving techniques that can further exploit the performance and enhance the reliability of GaN power devices. Topics to be covered include intelligent gate driving schemes such as active gate driving, dead time optimization, and current balancing. Emphasis will be given to designs that can be integrated and those that can monitor the devices for optimum performance and safe operation. Protection features such as short-circuit detection, gate overvoltage prevention, temperature monitoring and compensation will also be discussed. Monolithic integration of power GaN ICs is an exciting area of development with increasingly sophisticated designs reported in recent years. Fully integrated GaN building blocks and state of the art designs will be addressed.

Smart Gate Driver ICs for GaN Power Transistors

Gallium nitride (GaN), one of the wide-bandgap compound semiconductors, has unique material properties such as high electron saturation velocity and high breakdown field. A two-dimensional electron gas (2DEG) formed at an AlGaN/GaN heterointerface via spontaneous and piezoelectric polarization effects exhibits high sheet density and high electron mobility. Using these features, transistors with various device topologies (lateral and vertical) have been developed for both RF and power electronics applications. Among them, AlGaN/GaN-HEMTs fabricated on a high thermal conductivity SiC substrate are most widely used in high-power RF amplifiers for radars, satellite communications, cell phone base stations, etc. Owing to the rapidly increasing demand for higher bandwidths in the next generation communication and higher resolution imaging systems, millimeter-waves (30 – 300 GHz) are expected to play a critical role. Accordingly, GaN-based power amplifiers that have a high gain, output power, efficiency, and linearity at millimeter-wave frequencies are required. The frequency performance of GaN-HEMTs has been successfully improved through aggressive device scaling, and the cutoff frequency (fT) of highly scaled GaN HEMTs reached a 450-GHz range, i.e., 3-4× higher than conventional devices. The high-frequency device scaling, however, comes at the expense of reduced transistor’s power density due to the limited voltage swing. To overcome a well-known performance trade-off of millimeter-wave transistors among operational frequency, power density, efficiency, linearity, and reliability, new III-N material platforms as well as novel transistor architectures were proposed. They include (1) new III-N barrier materials such as AlN, InAl(Ga)N, ScAlN utilizing a larger polarization effect, (2) an Al composition graded AlGaN channel, (3) N-polar GaN-HEMTs, and (4) multiple 2DEG channels with a lateral gate. In this talk, I will discuss the progress of GaN-based high-frequency transistor development and technical challenges and introduce our new approaches on multiple 2DEG channel HEMTs with a buried dual gate (BRIDGE HEMTs).

High-Frequency GaN-Based Transistor Technologies: Progress and Future

Power design engineers want simplicity and the maximum degrees of freedom in making choices for the design challenges they face every day. They don’t want transistor suppliers to predefine the operation of a circuit in ways that may limit their approach to maximizing performance. Power designers want to innovate, optimize and not be constrained. There will always be a need for a mix of discrete, multi-chip packages, and power module form factors in order to meet the growing number and variety of GaN applications.

Downloads

Next from IEEE WiPDA 2021

Critical Design Considerations for Static and Dynamic Performances on 6.5 kV 4H-SiC MOSFETs Fabricated in a 6-inch SiC Foundry

Similar lecture

Increased 3rd Quadrant Current Handling Capability of 1.2kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances