United States

In this paper, a comprehensive comparative analysis is performed on the short circuit (SC) withstand time and failure modes between a 650 V SiC Planar MOSFET, a 650 V SiC Trench MOSFET and a 650 V SiC Cascode JFET. The short circuit tests have been performed at a DC link voltage of 400 V with gate turn-OFF voltages at 0 V and -5 V. The results show that the SiC Cascode JFET failed in a source-to-drain short circuit with the gate still capable of blocking voltage while the SiC Planar and Trench MOSFETs failed with the Gate-Source (VGS) terminal short circuited and Drain-Source (VDS) terminals still capable of blocking voltage. Furthermore, short circuit withstand times measured on the SiC Planar and Trench MOSFETs showed an increase (20% for the Planar MOSFET and 9% for the Trench MOSFET) when the device gate voltages were turned-OFF with -5V compared to 0V. This was due to the increased inductance of the negative voltage gate driver reducing the peak short circuit current. In the case of the SiC Cascode JFET, there was no dependence of the short-circuit withstand time on the VGS turn-OFF voltage.

IEEE WiPDA 2021

Comparison of Short Circuit Failure Modes in SiC Planar MOSFETs, SiC Trench MOSFETs and SiC Cascode JFETs

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
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Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

poster

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

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The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

This paper presents a FPGA-based real-time emulator
of silicon carbide (SiC) metal-oxide-semiconductor fieldeffect
transistor (MOSFET) employing dynamic device model.
The threshold-based model utilizes the Shichman and Hodges
equations with voltage-dependent non-linear device capacitances
to obtain an accurate model for the turn-on switching transients
of the device. Accurate dynamic switching behavior including
the key states drain-current, drain-source voltage and gate-source
voltage can be achieved in real-time and monitored with a digital
to analog converter. Such models are beneficial for rapid and costeffective
manufacturing of high-power SiC-based converters. The
simulation results are verified experimentally on a 3.3kV SiC
MOSFET module, showing good correspondence.

Real-Time FPGA Simulation of Silicon Carbide MOSFETs

6.5 kV-rated 4H-SiC MOSFETs have been successfully fabricated and demonstrated on 60 µm-thick, 1.2×1015 cm-3 doped N-type epi-layer on 6-inch, 4H-SiC N+ substrates. Devices were fabricated at the 6-inch SiC foundry, X-FAB, TX, USA. Active and edge termination areas of high voltage (>3.3 kV) SiC devices require critical design consideration due to implant straggles from the low background doping concentration. Despite the fabrication and design challenges, we have demonstrated Ron,sp of 47 mΩ-cm2 with a breakdown voltage of 7.9 kV with a very low leakage current using ring-based edge termination structure. Devices were then diced and packaged in a SUNY Poly’s custom-made package to evaluate short circuit capabilities. Short circuit withstand time of 6.2 µs was recorded from the nominal device, along with 7 µs and 13 µs from the device with narrower JFET width and wider channel length, respectively.

Critical Design Considerations for Static and Dynamic Performances on 6.5 kV 4H-SiC MOSFETs Fabricated in a 6-inch SiC Foundry

This talk discusses the dynamic characterization of a 3.3 kV SiC-based reverse voltage blocking switch for three different switch configurations used for the current source inverter (CSI). The static characterization of the devices is done for the latest generation 3.3 kV SiC MOSFET and diode. Based on these results, a preferred current switch is suggested for a medium voltage CSI.

Performance Evaluation of 3.3 kV SiC MOSFET and Schottky Diode for Medium Voltage Current Source Inverter Application

For efficient converter design, modeling of switching components must be both accurate and fast. A variety of simulation models
for SiC Power MOSFETs has been developed. To achieve adequate accuracy, models are adjusted to experimental data by applying fitting methods. However, proposed universal fitting methods result in high-dimensional optimization problems. Their computational inefficiency leads to either long run times or low accuracy. This paper proposes a new universal parameter fitting method that is at least twice as fast and yields a more accurate outcome than presented methods under comparable conditions. It effectively reduces the dimensionality of the parameter fitting optimization problem by sensitivity-based reduction of optimization parameters.
Thereby, it optimizes both model adjustment speed and accuracy, which are critical factors for an efficient converter design process. The method does not compromise flexibility as it is universally applicable to any SPICE model and can meet any model architecture preference.

Smart Universal Parameter Fitting Method for Modeling Static SiC Power MOSFET Behavior

This paper presents a method that extracts junction temperature of SiC MOSFETs by measuring a unique turn-on delay. In preceding work, the turn-on delay was identified as a particularly promising temperature-sensitive electrical parameter for SiC MOSFETs. The reasons for this are its simple calibration, its insensitivity to the device current, its linear temperature dependency as well as the particular behavior of the charge carrier mobility of SiC. However, state-of-the-art extraction circuits for turn-on delay only work with a limited time resolution. Thus, they can only be applied to slowly switched SiC MOSFETs. This work proposes a circuit for turn-on delay extraction with a time-to-digital converter that allows the time resolution to be significantly increased. Thereby, the circuitry allows utilizing turn-on delay as an effective temperature-sensitive electrical parameter for junction temperature extraction of SiC MOSFET operated with fast switching transients. The feasibility of the approach is experimentally validated in this work with a developed extraction circuit using a SiC MOSFET power module as a device under test.

Online Junction-Temperature Extraction Method for SiC MOSFETs Utilizing Turn-on Delay

Integrated circuits made using GaN-on-Si substrates have been in production for over seven years. During that time, GaN-based ICs have evolved from pure discrete devices to monolithic half-bridge devices and then onto power FETs that included their own monolithically integrated driver, and more recently, to fully monolithic power stages including power FETs, drivers, level shifting circuits, logic, and protection. In this talk we will look at the roadmap of GaN-on-Si integration and show how the role of discrete transistors is destined to diminish to near-zero in the next few years.

Gallium Nitride Integration and the End of Discretes

GaN power HEMTs are known to offer high switching speed, low on-resistance and much better FOM when compared to their silicon counterparts. However, the ability to operate with high power density in a smaller form factor presents new challenges for reliable and robust operation. Traditional gate driver designs for silicon-based power devices are catered to lower frequencies with large tolerance on the gate voltage swing. They do not adequately address some of the reliability issues that are unique to GaN power transistors. This talk will provide a quick review on the gate driving requirements and limitations for GaN power HEMTs. This is followed by a survey of novel smart gate driving techniques that can further exploit the performance and enhance the reliability of GaN power devices. Topics to be covered include intelligent gate driving schemes such as active gate driving, dead time optimization, and current balancing. Emphasis will be given to designs that can be integrated and those that can monitor the devices for optimum performance and safe operation. Protection features such as short-circuit detection, gate overvoltage prevention, temperature monitoring and compensation will also be discussed. Monolithic integration of power GaN ICs is an exciting area of development with increasingly sophisticated designs reported in recent years. Fully integrated GaN building blocks and state of the art designs will be addressed.

Smart Gate Driver ICs for GaN Power Transistors

Gallium nitride (GaN), one of the wide-bandgap compound semiconductors, has unique material properties such as high electron saturation velocity and high breakdown field. A two-dimensional electron gas (2DEG) formed at an AlGaN/GaN heterointerface via spontaneous and piezoelectric polarization effects exhibits high sheet density and high electron mobility. Using these features, transistors with various device topologies (lateral and vertical) have been developed for both RF and power electronics applications. Among them, AlGaN/GaN-HEMTs fabricated on a high thermal conductivity SiC substrate are most widely used in high-power RF amplifiers for radars, satellite communications, cell phone base stations, etc. Owing to the rapidly increasing demand for higher bandwidths in the next generation communication and higher resolution imaging systems, millimeter-waves (30 – 300 GHz) are expected to play a critical role. Accordingly, GaN-based power amplifiers that have a high gain, output power, efficiency, and linearity at millimeter-wave frequencies are required. The frequency performance of GaN-HEMTs has been successfully improved through aggressive device scaling, and the cutoff frequency (fT) of highly scaled GaN HEMTs reached a 450-GHz range, i.e., 3-4× higher than conventional devices. The high-frequency device scaling, however, comes at the expense of reduced transistor’s power density due to the limited voltage swing. To overcome a well-known performance trade-off of millimeter-wave transistors among operational frequency, power density, efficiency, linearity, and reliability, new III-N material platforms as well as novel transistor architectures were proposed. They include (1) new III-N barrier materials such as AlN, InAl(Ga)N, ScAlN utilizing a larger polarization effect, (2) an Al composition graded AlGaN channel, (3) N-polar GaN-HEMTs, and (4) multiple 2DEG channels with a lateral gate. In this talk, I will discuss the progress of GaN-based high-frequency transistor development and technical challenges and introduce our new approaches on multiple 2DEG channel HEMTs with a buried dual gate (BRIDGE HEMTs).

High-Frequency GaN-Based Transistor Technologies: Progress and Future

Power design engineers want simplicity and the maximum degrees of freedom in making choices for the design challenges they face every day. They don’t want transistor suppliers to predefine the operation of a circuit in ways that may limit their approach to maximizing performance. Power designers want to innovate, optimize and not be constrained. There will always be a need for a mix of discrete, multi-chip packages, and power module form factors in order to meet the growing number and variety of GaN applications.

One Size Doesn't Fit All - The Need for Multiple Approaches to GaN Circuit Design

The adoption of high voltage GaN on Silicon power devices is accelerating at a rapid pace over the last several years. The key for designers and system insertion has been robust and reliable, easy to interface and design, high performance normally off GaN compatible with multiple controller and driver architectures. With complete control of the core GaN materials and wafer technology as well as manufacturing, Transphorm’s high speed-high efficiency-easy to use SuperGaN FET with a proven field reliability (FIT < 0.4) products provide superior solutions for applications ranging from 30 Watts to 10 kiloWatts, today and already shipping in volume. This talk will review the growing use of GaN in markets like Fast chargers/adapters (lower power) to server, gaming, crypto mining, industrial (mid-high power) to renewables, energy and electric vehicles (high power), targeting 200% year over year growth.

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Real-Time FPGA Simulation of Silicon Carbide MOSFETs

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