United States

In this talk, we will cover the front-end reliability aspects and challenges that come along the imminent shift towards Gate-All-Around based MOSFETs architectures in cutting-edgelogic technologies. Additionally, we explore innovative architectural derivatives, like Forksheets FETs, towards continued logic cell downscaling. The tutorial extends to the distinctive integration challenges posed by these devices, and we will examine their impact on both time-zero and time-dependent performance, including dielectric walls for N-to-P separation and device substrate isolation.

IRPS 2024 Tutorials and YIR

Reliability Aspects of Nanowire, Nanosheet and Forksheet Devices

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

tutorial

**IRPS 2024 Tutorials were held in Dallas, Texas from April 14 to 15, 2024. The IRPS Reliability Year in Review (YIR) session consisted of three presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It was a nice augmentation to the tutorials sessions immediately preceding and attendees were able to obtain keen reliability insights in short amount of time.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/31e631d9941728874f1cea6ddf221cd4.png)](https://underline.io/events/445/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/a6a3fb1b1830527791842ee5c8f13e6c.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/35139d437e3e8a3413aa4c1f0d2c5400.png)](https://drive.google.com/drive/folders/1Iy0QiBLQlf17nt_xBrqLLvY9_rPaFhDn?usp=sharing)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**
Please save the zip file locally and click the "start.pdf" to view the file. 

**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Thanks to its superior switching properties, GaN is penetrating several power applications resulting in highest efficiency and system miniaturization. In this seminar, we’ll review the key device technologies (e-mode and cascode) and discuss their trade-offs between performance and reliability. We will show how to achieve high voltage rating up to 1200V and short-circuit capability up to 5 microseconds. The main topologies and applications will be presented, discussing good practices to use GaN fast, but reliably.

GaN Power Device Technology and Reliability

This tutorial covers 6 main topics:

Basic data types used in the field of reliability

Basic distribution functions and its application

Main lifetime models, their use and their properties

Basic fitting methods used in fitting reliability data to the most suited distribution and lifetime model

Basic ways to display distributions, lifetime models and their fits

Some more advanced statistical models to account for variability issues in advanced devices

Introduction to Statistics for Reliability

This tutorial will cover basic mechanisms, differentiating between transient and permanent shifts in threshold voltage (VT), and discussing the impact of such instability on device reliability and performance. Specific topics will include: VT shift versus VT drift and hysteresis, and how to measure both static and dynamic instability; dependence on measurement speed, bias, and temperature; degradation and VT shift; bias-temperature stress degradation; gate-switching (AC) stress degradation; dynamic on-state resistance; and other related effects and analysis.

Threshold-Voltage Instability in SiC MOSFETs

Resistive switching memory (RRAM) technology is a promising resource in the landscape of neuromorphic computing applications. In fact, RRAM can provide a convenient primitive for matrix-vector multiplication with a strong impact on the acceleration of Deep Learning. However, RRAM is affected by intrinsic conductance variations which might cause short- and long-term reliability issues. This tutorial will present a multiscale approach, ranging from the device to the circuit level, to mitigate those issues for accelerator design.

Reliability of RRAM Technology in the Context of Neuromorphic Applications

Defect localization is key to device improvement, yield management, and reliability fail characterization.  How do you isolate defects when your fails are blowouts? How does one choose an FA technique form the alphabet soup of techniques? This tutorial will offer an overview of a wide variety of electron, ion, and laser-based fault isolation techniques from decades of fab experience and cutting-edge technique development in microscopy development. 

Defect Localization Methods for Device Characterization and Yield Management

This tutorial aims at presenting an overview of degradation phenomena that lead to dielectric breakdown. We discuss how dielectric degradation can be observed and show possible consequences for device operation. An important aspect of TDDB is a correct description of its statistics, that can be derived from individual defect generation dynamics. We look at modeling approaches and ways of calculating the time-to-breakdown. We also discuss differences and similarities of breakdown in FEOL, MEOL and BEOL.

Understanding and modeling Time-Dependent Dielectric Breakdown

Technology Computer Aided Design (TCAD) tools are well established for modeling semiconductor fabrication processes, and device operations. This tutorial provides an overview how TCAD can is for modelling of various reliability issues, including mechanical stresses introduced during manufacturing process or device operations, Electrostatic Discharge (ESD), latch up/junction breakdown, Hot Carrier Degradation (HCD) and Negative Temperature Bias Instability (NTBI) and Time Dependent Dielectric Breakdown (TDDB), modeling of charge loss mechanics in 3D NAND memories, and others.

TCAD for Reliability

Two-dimensional (2D) materials possess various intriguing properties, making them promising building blocks for future nanoelectronics. For example, 2D semiconductors offer sizable mobilities and high on-currents in thin layers, allowing for excellent gate control in scaled transistors. Nonetheless, to bridge the gap between current device prototypes and commercial applications, multiple challenges must be overcome, including identifying gate stacks that are both scalable and allow for reliable operation throughout the device’s lifetime.

Reliability of Nanoelectronics based on Two-Dimensional Materials

In this tutorial, I will give a brief introduction to reliability and failure analysis fundamentals; review key reliability aspects for SiC devices such as bias temperature instability, bipolar stability due to Shockley stacking faults, gate oxide reliability, humidity effects, reverse bias, single event burnout and power cycling; illustrate mission profile analysis techniques; review essential failure analysis techniques such as fault detection, FIB/SEM and EBIC; and review the latest industry consortia standards and guidelines.

SiC Device Reliability and Failure Analysis

Design Technology Co-optimization (DTCO) has become a critical part for new technology development and applications.  For high end and critical application products, reliability co-optimization is an important integral part of DTCO.  This tutorial focus on the interconnect reliability optimization considerations for chip design.  Discussions will be made from understanding the intention and limitation of various design guidelines & reliability limits to identifying critical areas and robust layouts for different interconnect reliability mechanisms for chip design.

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