United States

In this work, we report the first comprehensive TDDB study on ultra-thin HfO2-based ferroelectric capacitors under bipolar stress conditions. Bipolar cycling of FE-HZO is shown to exhibit similar TDDB acceleration trends to that of traditional dielectrics. The temperature acceleration of TDDB shows a linear dependence on the stress field similar to SiO2. The field acceleration of TDDB in FE-HZO, while exhibiting functionally similar temperature dependence to that of SiO2, demonstrates considerably greater sensitivity to temperature.

IRPS 2024 Main Conference

Comprehensive time dependent dielectric breakdown (TDDB) characterization of ferroelectric capacitors under bipolar stress conditions

bipolar field stress

ferroelectric tddb

hfo2 based ferroelectrics

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

technical paper

Reliability of the clock signal is critical for the system in the nanometer technology. Duty cycle is one of the key metrics in the performance of clock signals. We explore the impact of wear out induced duty cycle shift in the local clock networks and propose adaptive clock gating for improving the reliability with the FinFET CMOS technology. The work demonstrates the duty cycle improvement during the lifetime with Intel FinFET technology.

Si Characterization of Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Local Clock Network

Neutron irradiation of Si and Ge photo-diodes has been performed at the n\_TOF facility at CERN. Transients are collected and compared to those generated by ultrafast laser. Deposited charge is characterized as a function of the neutron energy.

Neutron and Laser Irradiation of Si and Ge Diodes

This paper introduces an essential on-chip architecture to characterize Random Telegraph Noise (RTN) accurately for modern integrated circuits (ICs), demonstrated through results from test structures in SkyWater Technology's 90 nm CMOS process. A comprehensive multi-step process, including a pre-processing scan of a 96x128 device array, offers insights into device variability and RTN, guiding more efficient CMOS design strategies.

On-Chip Characterization of Random Telegraph Signal Noise in Bulk 90 nm CMOS

It is very important to predict cell oxide wear out life. The lifetime is determined by the degradation of the cell oxide due to the stress. It is necessary to identify the stress that the cell receives and accurately reproduce it in the evaluation. In this paper, the stress situation that cell oxide receives was analyzed through energy band and electric field strength of oxide, and an accurate prediction methodology for oxide lifetime was studied.

A valid experimental design of the lifetime prediction for NAND Cell Oxide

The mixed-mode reliability of Silicon Germanium HBTs is investigated down to 25K. Results suggest that damage (monitored by base current leakage) increases to a peak around 100K and then decreases. Results also show a not-before-reported shift in collector current from DC electrical stress, which is visible at cryogenic temperature and occurs regardless of the temperature the device is stressed at.

Anomalous Mixed-Mode Damage Effects in SiGe HBTs at Cryogenic Temperatures

In this paper, the impact of hot-carrier injection due to repetitive pulse switching of lateral DMOS transistors is studied. The proposed testing technique is used to emulate the dynamic switching conditions and the transistor reliability characteristics are compared with traditional DC measurement at constant gate/drain voltages. Experimental data shows that the repetitive pulse degradation under 6.6V drain stress is between two DC conditions (5.5V and 6.6V).

Repetitive Pulse Testing for LDMOS Transistor Reliability

The impact of scaling on the effects of mixed-mode electrical stress and ionizing radiation is assessed for third- and fourth-generation SiGe HBTs. When the devices were operating in forward-active mode, the fourth-generation technology showed a better radiation tolerance but worse hot carrier degradation due to mixed-mode stress. However, when the devices were operating in inverse-active mode, the trend was the opposite and the fourth-generation technology showed worse radiation tolerance but less mixed-mode degradation.

The Impact of Scaling on the Effects of Mixed-Mode Electrical Stress and Ionizing Radiation for 130-nm and 90-nm SiGe HBTs

In this work, H3TRB testing is conducted to compare the accelerated failure of vertical SiC power MOSFETs provided by two-well known manufacturers. A pronounced drain-to-source leakage is observed in tested devices from only one of the manufacturers, which is associated with a surface charge accumulation near the edge-termination structure of the device. Failure analysis of the device and package encapsulant is conducted to investigate the failure/degradation mode and to better understand the reliability physics. 

Surface Charge Migration in SiC Power MOSFETs Induced by High-Voltage H3TRB Testing

The geographical dispersion of manufacturing units makes real-time data aggregation a challenging task, especially as the scale of operations continues to expand. Moreover, manufacturers deal with sensitive and proprietary data and are reluctant to share data directly in areas such as lithography hotspot detection (LHD) due to concerns about IP protection. In this regard, In this work, we propose a QFL framework for LHD and offer a unique solution to address the aforementioned challenges effectively.

Robustness of Quantum Federated Learning (QFL) against “Label Flipping Attacks” for Lithography Hotspot Detection in Semiconductor Manufacturing

Silent Data Errors (SDE) are a unique category of errors that result in unpredictable system behavior that is often difficult to detect. SDEs can represent a serious concern to at-scale compute in data center operation. [1,2] This paper reviews data collected on SDE impacts to Artificial Intelligence (AI) workloads and Intel’s SDE mitigation tools available for use in the data center.

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Si Characterization of Adaptive Clock Gating for Improving Wear out induced Duty Cycle Shift in the Local Clock Network

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