United States

As compute node density increases exponentially in data centers, silicon faults undetected by the machine check architecture must be tightly managed. While many undetected faults will result in an application crash or a detected uncorrected error, those that manifest as silent data errors (SDE) are of greater concern because they may cause data loss or data corruption. We report the first detailed defect characterization regarding the types of defects that lead to SDE events.

IRPS 2024 Main Conference

Defect Mechanisms Responsible for Silent Data Errors

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

poster

In this paper,we have developed a new convolution-based methodology to estimate the dynamic time-evolutionary degradation of pixel circuits in display applications. For the first time, we have enabled real-time observation of the threshold voltage changes over time in key driving TFTs under different bias conditions in transient simulations of pixel circuits. Additionally, we introduce an optimized 9T2C pixel compensation circuit,which is an approximately 50% improvement over the 0.73μA observed in the 7T1C configuration.

Convolution-Based Vth Shift Prediction and the New 9T2C Pixel Circuit in LTPS TFT AMOLED

Sentaurus TCAD is enabled to simulate parametric shift due to BTI and HCD in p-andn- GAASNSFETs.The framework is calibrated using ultra-fast measured BTI data at different VG andT, and HCD data at different VG and VD during and after stress.The isolated BTI and intrinsic HCD contributions are used in a cycle-by-cycle circuit simulation framework to determine Ring Oscillator(RO) degradation at various VDD, Tand Dynamic Voltage and Frequency Scaling(DVFS) conditions.The End-of-Life(EOL) device and RO degradation are compared.

A TCAD to SPICE Framework for Isolation of BTI and HCD in GAA-SNS FETs and to Estimate Impact on RO Under Normal and Overclocking Conditions

This paper integrates the commonly used reliability HCI models in the industry. Through VRS and silicon verification, the comparable results to CVS can be obtained.  And a novel VRS-analyzer for process limits and accelerated testing voltage is proposed, which can also be used to assess the health of dynamic voltage stress (DVS) voltage. This method can improve evaluation speed and reduce stress energy by about 10X.

A Comprehensive Hot Carrier Injection with Voltage Ramp Stress (HCI-VRS) through different model verification for more than Moore diversity application

Sheet/channel wrapping by low-thermal conductive material, sheet-stacking, and dielectric wall (DW) for N/P separation puts reliability concerns in Forksheet FET. Using TCAD we analyzed (i) the role of self-heating-effect within N/P and beyond DW; (ii) impact of random dopant fluctuation on ION and Vth (iii) impact of metal- grain-granularities and ratio of grain-size to gate area (RGG) on Vth and finally (iv) the benchmarking of devices’ aging, i.e., lifetime-prediction (LTP), defined by Vth = ±50mV.

Self-heating and Process-Induced Threshold Voltage Aware Reliability and Aging Analysis of Forksheet FET

Non-conducting hot carrier can induce significant drift of MOS transistor parameters especially at high temperature which is found to be worst case. We show here that activation energy account not only for defect generation mechanisms temperature activation but also for significant temperature sense effect.

Non-conducting Hot carrier temperature activation and temperature sense effect

ADC circuits may cause RTS column signatures in 3D stacked CMOS image sensors. This work proposes a statistical and design evaluation of RTS for 40nm node devices, used in ADC circuits. A transistor array mimicking 3T CIS pixel array architecture is used for RTS characterization, with a proposed RTS detection methodology and counting. The designs presented exhibit a noteworthy decrease in the number of RTS occurrences, as evidenced by the experimental results.

Design Techniques Evaluation to Mitigate RTS Noise Effect in Column ADC of 3D Stacked Image Sensors

We present HBp-index, a novel quantitative model that explains the combination effect of hydrogen and process heat on peripheral transistors in 3D NAND flash memory. We observed the index linearly matched with the change of electrical characteristics of the transistors for various heat processes. Furthermore, we found the NBTI life time of the peripheral transistors increased by 90mV, which is due to the expansion of the poly-depletion region by increasing hydrogen concentration during cell fabrication.

A Novel Quantitative Model for Combination Effects of Hydrogen and Process Heat on Peripheral Transistors in 3D-NAND Flash Memory

The effect of Off-state stress on a propagation delay (tPD) and a data-valid window (tDV) was characterized. The Vth reduction of PMOSET due to the electron trapping into the nitride in the STI, resulting in the decrease of tDV. The extracted time slope of ∆Vth and ∆tDV showed same ~0.4. It indicates that the degradation was dominated by the off-state stress. The mechanism was investigated by varying the process, and an empirical model was proposed.

Effect of Off-State Stress on Data-Valid Window Margin for Advanced DRAM using HK/MG Process Technology

We report a non-monotonical temperature dependence of hot carrier injection (HCI) degradation for 14 nm Si FinFETs operated at low temperature (LT). An HCI model including multiple-particle single-particle and oxide traps was proposed to separate the effects from different traps. As stress time increases, the dominant traps switched from single-particle traps to oxide traps, and as temperature reduces, oxide traps and single-particle traps will make more contributions to the HCI degradation.

Low Temperature Characterization and Modeling of Hot Carrier Injection in 14 nm Si FinFET

We reveal that negative body bias stress significantly enhances carrier energy near the bottom of the Fin, consequently exacerbating HCD in nFinFET. Furthermore, with the increase in negative body bias stress, the proportion of traps at the bottom of the Fin gradually increases, consequently weakening the body bias modulation effect. We introduce a novel characterization technique that employs body bias modulation of Vth to differentiate the distribution of traps within the vertical Fin direction.

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