United States

In this work co-optimization of Silicon controlled rectifier (SCR) ESD characteristics with its low voltage trigger circuit is presented.  The low trigger circuit design approach is discussed and presented. In the process we find that some of the trigger circuits previously reported in literature do not work as desired until co-optimization device engineering techniques are used. The circuit insights are explored using well calibrated electrothermal 3D process and device TCAD mixed mode simulations.

IRPS 2024 Main Conference

Missing Trigger Circuit Action and Device Engineering for Conventional Nanoscale SCR

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

poster

Devices used in space detection may operate at 600 K, so latches can occur in extreme environments. Through experiments and TCAD simulation, the leakage current mechanism is analyzed in this paper. The proposed analytical model can perfectly predict the latch-up voltage. Both self-heating and leakage current can be suppressed using the back gate bias, which also increase 1/f noise. The influence mechanism of the back gate was verified through TCAD.

Research on the Latch-up Mechanism of DSOI at High Temperature

We investigate the role of gate hole injection in reducing the charge trapping in AlGaN/GaN HEMTs submitted to semi-on stress at grounded, negative, and positive substrate bias. Injected holes are retained by ionized carbon acceptors within the SCR region in UID/C:GaN when a negative substrate is applied, suppressing the capacitive coupling between substrate and 2DEG that is responsible for channel depletion. The role of substrate bias in modifying the internal field distribution is discussed.

P17.GaN -Role of Gate Hole Injection in Minimizing substrate Coupling and Electron Trapping in AlGaN/GaN Power HEMTs

The integrated circuits must be verified through latch-up test, according to the JESD78F.01 standard. This work presented a specific latch-up challenge encountered in an IC product, where a multi-functional I/O buffer suffered latch-up failure, due to the indirect connection on the N-well of output PMOS to the power supply through a bias switch. By using an embedded deep-nwell collector, the latch-up immunity of such a multi-functional I/O buffer can be significantly improved.

Embedded Deep-Nwell Collector used to Improve Latch-up Immunity of Multi-functional I/O Buffer with Indirect Power-Connected N-Well

A new thermal model for GaN/GaAs FETs has been developed that provides temperature estimates of individual gate fingers. The model assists in simulating scaled transistor performance and aging quickly and accurately. It provides designers with more flexibility as thermal resistance is automatically adjusted with gate periphery and gate-to-gate spacing, including non-uniform spacing.

Fast, Scalable, and Highly Accurate Thermal Modeling for Use in GaN/GaAs RF Circuit Modeling Platforms

In this work, based on detailed experimentation, we probe the physical mechanism behind the dependence of device performance and reliability on the intrinsic stress in passivation. By engineering the passivation stress to a higher compressive value, we have achieved an improved device performance in terms of 500mV positive Vth shift, enhanced DC breakdown voltage by 105V along with the improved dynamic RON performance. 

On the role of stress engineering of surface passivation in determining the device performance of AlGaN/GaN HEMTs

Cross temperature effect is a fundamental reliability concern for 3D NAND Flash memory. In this paper we explore the origin of cross temperature reliability by measuring the cell threshold voltage (Vth) distribution at different temperatures. We observe significant cell-to-cell variability in the temperature coefficients causing distribution widening. We provide a conceptual picture to model the distribution widening based on sub-threshold slope factor variation. We also discuss two system level countermeasures to minimize the cross-temperature effects.

Cross-Temperature Reliability of 3D NAND: Cell-to-Cell Variability Analysis and Countermeasure

A novel vertical channel DRAM cell array transistor has been proposed and verified. A back gate shared by adjacent two word lines has been introduced to have both word line disturb immunity and threshold voltage controllability, while having a small foot print and corresponding scalability. The increased word line coupling has less effect on overall word line disturb immunity, by virtue of insignificant passing gate effects and reduced variability.

Effect of Back Gate on Word Line Disturb Immunity of a Vertical Channel DRAM Cell Array Transistor

Two oxidation methods to optimize the BE SiON. Molecular-mode oxidation operates in a diffusion-based manner, leading to deeper oxidation throughout the entire SiON. In contrast, radical-mode oxidation, classified as an exchange-mode process, primarily targets the SiON surface. Using our 3D AND-type NOR Flash memory, both molecular and radical oxidation techniques were applied to the BE-MANOS device for chip-level reliability study. Both molecular and radical oxidation shows obvious improvements (15-25%) on post-cycled retention performances.

Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide

In this study, the relationship between the interface trap generation and MOSFET degradation under high voltage F-N stressing at 77 K ~ 300 K. As results, respective ΔDit and ΔIon are suppressed with decreasing temperature irrespective of the stress polarity. However, the correlation between ΔDit and ΔIon is more serious at lower temperature compared to that at higher temperature. It is inferred that the additional degradation mechanism is working at lower temperature region.

Re-consideration of Correlation between Interface and Bulk Trap Generations using Cryogenic Measurement

This paper investigates the impact of body bias (VBS) on ION degradation in SiGe-channel pMOS without Si-cap for DRAM periphery. Experimental data show SiGe-channel devices have higher ION degradation under VBS-stress. In this paper, we investigate the ION degradation mechanisms using TCAD. Narrower bandgap of SiGe-channel causes higher electric-field, resulting in higher traps at the SiGe–SiO2 interface. Different VTH SiGe-channel devices are studied to understand the impact of channel doping on electric-field inside the devices.

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Research on the Latch-up Mechanism of DSOI at High Temperature

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