United States

This talk focuses on aging and self-heating effects in transistors. As technology nodes shrinks, 3D structures become more confined and less reliable. We showcase how deep learning and machine learning techniques offer innovative solutions for the EDA industry. These techniques enable designers to estimate the impact of these phenomena without the need for divulging confidential models. We demonstrate the seamless integration of sign-off tools to estimate self-heating in an entire processor at the GDS level.

IRPS 2024 Main Conference

Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor

cell libraries

processor

aging

self-heating

machine learning

reliability

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

technical paper

This paper characterizes the aging of a digitally controlled inductive voltage regulator (IVR) in 65nm CMOS due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI). Measurements show that aging degrades transition speed, regulation quality, and efficiency, and the aging of the feedback loop dominates performance degradation.

Measurement of Aging Effect in a Digitally Controlled Inductive Voltage Regulator in 65nm

Cryogenic CMOS suffers excessive self-heating (SH), which is a major
concern for quantum computing. This work reveals the 
impact of SH in cryogenic circuits, from the transistor
level to the processor level, using 28nm FDSOI. We first extend the
industry-standard BSIM-IMG model to incorporate the
cryogenic temperature-specific transistor characteristics. The
calibrated model is employed to create standard cell libraries, which are
deployed to analyze complex circuits inducing
processor.

On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth analysis from Transistors to Full Processor

In this work, we investigated the reversible and irreversible polarization degradation of hafnia-based ferroelectric capacitors (FeCAPs). The main observations are as follows: (1) The temperature-dependent orthorhombic (o-) and tetragonal (t-) structures with coherent phase boundary (CPB) moving corresponds to the reversible polarization changes of hafnia-based FeCAPs with temperature, i.e., the o-t (t-o) coherent structural transition. (2) The polarization degradation caused by o-/m-CPB migration with temperature is irreversible.

Reversible and irreversible polarization degradation of Hf0.5Zr0.5O2 capacitors with coherent structural transition at high temperature

Data retention measurements are performed on HZO-based BEOL-integrated scaled FeCAPs and 16kbit 1T-1C FeRAM arrays for the first time. At FeCAP level, Opposite State retention is strongly degraded by imprint. Imprint is found to be write-voltage independent, showing great promises for FeRAM voltage scaling with adequate write/read voltage distinction. At FeRAM-array level, post-bake distributions show SS and OS drifts that are consistent with FeCAP. These drifts are attributed to imprint and recoverable through bipolar cycling.

Data Retention Insights from Joint Analysis on BEOL-Integrated HZO-Based Scaled FeCAPs and 16kbit 1T-1C FeRAM Arrays

We present a new framework for accurate reliability modeling of NVDRAM – a 32Gb HfZrOx-based 1T1C ferroelectric memory technology for DRAM-like applications. We report array-level characterization and modeling of a) imprint, b) fatigue, c) a new failure mode from bipolar AC TDDB, and (d) a new degradation mechanism of frequency-dependent accelerated polarization loss. Unlike existing literature, the proposed framework combines the worst-case of all degradation mechanisms and can predict product lifetime accurately.

Comprehensive Reliability Assessment of 32Gb (Hf,Zr)O2-Based Ferroelectric NVDRAM

The 2D transient electrothermal-mechanical and metallurgical model of a 1.2kV-80mohm SiC MOSFET in a single FEM software, created previously by the authors, has been developed. This model aims to quantify the short-circuit critical time and energy density of attaining the local interlayer strength and the Al source-metal phase transition at elevated temperatures. The novelty is considering electrothermal and non-linear elastoplastic material property laws over a wide range of temperatures and verified experimentally.

A Full Transient ElectroThermal - Elastoplastic Mechanical and Metallurgical 2D FEM of SiC MOSFET for Gate-Region Stress Investigation under Short-Pulse Short-Circuit

We investigate the degradation of 4H-SiC MOSFETs after experiencing negative threshold shift from high voltage gate stress and after further stress to restore the threshold voltage near its original value. Charge pumping measurements show a clear increase in total interface trap density after each stress, but no change near the band edges. Moreover, a buildup of net charged oxide trap density of about 3×1012 cm-2 after stress is deduced from the shift in flatband voltage.

Characterization of Interface Trap Density in SiC MOSFETs Subjected to High Voltage Gate Stress

This work improves the understanding of charge trapping in SiC MOSFETs during constant gate current stress, with charge-pumping and threshold voltage measurements. A custom-made, on-wafer measurement setup was used. Gate voltage varied non-monotonically during stress, showing different charge-trapping mechanisms: a) electron trapping at near-interface oxide traps; b) hole trapping, due to impact ionization in the oxide; c) generation of electron traps at the interface. Charge pumping measurements quantitatively described interface traps long term variation.

Charge Trapping in SiC MOSFETs under Constant Gate Current Stress: Analysis Based on Charge Pumping Measurements

Chalcogenide-based self-rectifying selector-only memory (SOM) concept has shown great potential for high-density high-performance applications. While very promising, the understanding of the physical mechanism behind the polarity effect is still lacking. This work provides an in-depth investigation of SiGeAsSe OTS-only memory and discusses its possible limitations to establish the underlying performance and reliability trade-offs. Additionally, we propose an updated electronic switching model, capable of qualitatively reproducing the polarity effect as well as observed reliability results.

Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory

A modeling framework to describe NBTI characteristics in GAA is proposed. Three dimensional simulations of Si-H bond de-passivation and re-passivation, hydrogen species generation and transport, interface and bulk trap generation, and threshold voltage shift are examined. The extracted voltage-acceleration factor and activation energy are in close match with GAA experimental data.  The impact of nanosheet thickness and SiGe channel on GAA NBTI characteristics are investigated and the model projections align very well with published reports.

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Measurement of Aging Effect in a Digitally Controlled Inductive Voltage Regulator in 65nm

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On the Severity of Self-Heating in FDSOI at Cryogenic Temperatures: In-depth analysis from Transistors to Full Processor