United States

The methodology and design behind TESCAN TENSOR - the world’s first Integrated, Precession-assisted, Analytical 4D-STEM will be presented. An advanced (electron diffraction) microscope, with STEM, 4D-STEM and STEM Tomography applications, TESCAN TENSOR will be shown to be the solution of choice for a range of nanoscale applications. These include multimodal characterization of functional materials, semiconductor thin films, and submicron, synthetic and natural particle crystals. Examples including results from battery and semiconductor device applications will be presented. Designed from the ground up to provide quality, throughput, and robustness of 4D-STEM acquisition, analysis, and processing, TESCAN TENSOR has been optimized with state-of-the-art technologies, such as Precession Electron Diffraction (PED), 4D-STEM computing and visualization, electrostatic beam blanking, and ultra-high vacuum at the specimen area. Additionally, TESCAN TENSOR features near real-time, automated data analysis, whereby on-the-fly processing presents first results during acquisition. As a result, TESCAN TENSOR allows the operator to focus on data acquisition and analysis, rather than time consuming manual microscope alignments. 4D-STEM phase and orientation analysis of lithium-ion battery anode materials. A precession-assisted, analytical 4D-STEM, TESCAN TENSOR, provides a solution for nanoscale phase and orientation mapping of phase separations and crystallographic ordering. Precession-assisted 4D-STEM was used to produce maps of LiTi2(PO4)3, TiO2 and LiTiOPO4 phases present in spindle-like battery anode particles. 4D-STEM phase analysis will be presented showing that TiO2 nanoparticles form a network at the LiTi2(PO4)3 sub-particle boundaries, which may provide a more effective diffusion pathway for lithium ions at higher cycling rates. Due to the fine polycrystalline nature of these networks, conventional phase analysis with TEM selected area diffraction or high-resolution imaging, is not practical. Additionally, the presence of titanium in both LiTi2(PO4)3 and TiO2 phases complicates robust identification of grains with EDX analysis. Multimodal phase and orientation analysis of complex semiconductor devices. For semiconductor manufacturers, it is desired to have comprehensive analytical capabilities, with the ability to measure chemical and structural properties, complementary to specimen morphology, down to the sub-nanometer scale. This is generally addressed using Energy Dispersive X-Ray (EDX) mapping, defect analysis through diffraction measurements, crystal orientation and phase mapping, and critical dimension imaging. These capabilities are important as the electrical performance of devices depends strongly on the type and distribution of crystalline phases in individual layers. Analytical electron microscopy, incorporating EDX, and phase/orientation analyses is therefore crucial for both process development and failure analysis. The TESCAN TENSOR analytical 4D-STEM provides a unique workflow interface to facilitate efficient chemical and structural analysis using EDX mapping, and precession-assisted phase and orientation mapping. The alignment and workflow automation enables effortless, automated switching between measurements optimized for STEM imaging, EDX analysis, or analytical 4D-STEM. While EDX maps are useful for rapid evaluation of elemental distributions, they cannot be used to conclusively determine phase distributions or segregations, this is instead investigated using precession electron diffraction assisted 4D-STEM. TESCAN TENSOR provides a solution for robust, multimodal, nano-characterization of complex semiconductor devices made up of multiple phases with real-time data analysis and processing for the benefit of process development and failure analysis.

EMC 2023

TESCAN TENSOR a 4D-STEM for Multimodal Characterization of Challenging and Interesting Specimens

precession

characterization

stem

We are pleased to announce the Fortieth AAAI Conference on Artificial Intelligence (AAAI-26), which will be held in Singapore EXPO from January 20 to January 27, 2026.

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AAAI 2026

We are pleased to announce the Fortieth AAAI Conference on Artificial Intelligence (AAAI-26), which will be held in Singapore EXPO from January 20 to January 27, 2026.

technical paper

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC). This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. 

We report on the growth and characterization of in-situ Al2O3 on (010) β-Ga2O3 deposited using metalorganic chemical vapor deposition (MOCVD) to enhance the dielectric quality and lifetime. The growth of Al2O3 is performed after the growth of β-Ga2O3 without breaking the vacuum in an Agnitron MOVPE reactor with far injection showerhead design using Trimethylaluminum (TMAl) and Oxygen as precursor gas. The interfacial dielectric layer (First 5 nm) is grown at 800 °C to crystallize the interface to have reduced interface trap density and the rest of the dielectric (17 nm) is grown at 600 °C. Thickness of the grown Al2O3 layer was extracted to be ~22 nm using Xray reflectivity measurements. Grazing incident Xray diffraction analysis was performed and polycrystalline inclusions were observed in the grown Al2O3 films. The dielectrics grown at 600 °C exhibited higher interface trap densities (Dt = 3.2×1012 cm-2) and lower breakdown fields (EBR=6 MV/cm) when compared to the dielectrics grown at 800 °C (EBR= 10 MV/cm, Dt=5.4×1011 cm-2) as is evident from the hysteresis and the trap density vs energy characterization which were determined using deep-UV assisted CV measurements and the current-voltage characteristics of the MOS capacitor test structures. The temperature-modulated dielectric sample (interfacial layer grown at 800 °C, and the bulk dielectric grown at 600 °C) has higher breakdown strength (EBR=7.7 MV/cm) and lower trap density (Dt = 1.1×1012 cm-2) compared to the dielectric grown at 600 °C. This is possibly due to the interfacial crystallization of the hybrid dielectric due to the initial growth at higher temperature. Time dependent dielectric breakdown (TDDB) (current vs stress time) was performed to characterize the long-term reliability of the grown dielectrics. From the Weibull distribution plots of the time to breakdown for four different TDDB stress conditions, a shape factor of β > 1 is observed which indicates good statistical uniformity and intrinsic breakdown behavior. The TDDB distribution is much tighter (higher β value) for the 600 °C dielectric, compared to the 800 C grown dielectric. This is possibly due to the short-range ordering of the 800 °C dielectric compared to the 600 °C dielectric, which reduces the long-term reliability of the dielectric. However, for the hybrid dielectric, the time to breakdown is found to be more tightly distributed when compared to both 600 °C & 800 °C dielectric. Based on the E-model (field-based model), the lifetime of the 800 °C can be extended to 10 years if the dielectrics are stressed at 0.7 MV/cm, whereas the lifetime of the hybrid dielectric can be extended to 10 years if it is stressed at 3.1 MV/cm. Thus although the static breakdown voltage and trap densities of the hybrid dielectric are a little inferior compared to the 800 °C dielectric, the long term reliability of the hybrid dielectric is much superior. This approach of in-situ dielectric deposition on β-Ga2O3 can pave the way for promising robust gate dielectrics for future β-Ga2O3 based high performance MOSFETs due to its promise of improved interface and bulk quality and long-term reliability compared to other conventional dielectric deposition techniques. We acknowledge funding from AFOSR MURI program under Award No. FA9550-21-0078 (PM: Dr. Ali Sayir).

B3/DD02 (Student) Enhancing the Dielectric Performance of Al2O3 on β-Ga2O3 Using Temperature Modulated in situ Dielectric Deposition

The increasing resistance of Cu interconnects for decreasing dimensions is a major challenge in the continued downscaling of integrated circuits as it leads to unacceptable signal delays and power consumption in computing. The resistivity of conventional metals (Cu, Ru, Co) increases due to electron scattering at surfaces and grain boundaries of the interconnects at the nanoscale. Thus, future energy-efficient computing technologies require breakthroughs in interconnect technologies, particularly in new interconnect materials. Topological semimetals are promising materials for low-dissipation on-chip interconnects as their topologically protected surface electrons are forbidden to backscatter. Here, we demonstrate that the unprecedented resistivity scaling of topological metal nanowires is competitive to those of effective Cu with barrier/liner and barrier-less Ru interconnects, suggesting topological metal (MoP, CoSi, WP) is an attractive alternative for the current scaling challenge of Cu interconnects and atomistic 1D topological material platform. (Reference) H.J. Han, S. Kumar, G. Jin et al., Topological Metal MoP Nanowire for Interconnect, Advanced Materials (2023) G. Jin et al., Nanoscale size-effects in 1D-confined transformation of tungsten phosphide nanowires, Submitted (2023) (Acknowledgements) G. J and J. C. C. gratefully acknowledge the support by the Semiconductor Research Corporation (SRC) – nCORE IMPACT center. J. C. C. acknowledges support from Betty & Gordon Moore Foundation under the EPiQS Investigator Award.

Dimensional Scaling of Topological Metal Nanowires for Interconnect

Polycrystalline diamond has excellent material properties such as high carrier mobility, excellent thermal and mechanical properties. Although polycrystalline diamond has been widely used as a surface protection layer, its practical use in electronic applications has been limited due to an unfavorable synthesis conditions. Polycrystalline diamond nanomembrane (PCD NM) is a different format of polycrystalline diamond film that is a free-standing form. The PCD NM is also a transferable diamond film that has a wide range of freedom in their thicknesses (a few tens of nm to hundreds of microns), size (micron-size to a full wafer scale), doping type/concentration, therefore, PCD NMs can be heterogeneously integrated with other foreign substrates or platform easily. In this talk, we will present our recent development of transferrable PCD NMs, including the NM synthesis and manipulation processes and their electrical properties. Fig.1(a) shows a schematic illustration of the creation of PCD NMs from the bulk PCD substrate. A 3um thick boron doped PCD thin-film was originally grown on a 2-inch SiO2/Si substrate via microwave plasma assisted chemical vapor deposition (MPACVD) growth reactors. In order to achieve a high-quality PCD thin-film, the pre-seeding process with diamond powder was performed prior to the growth. Once the PCD growth was completed, an array of etching holes was formed to access the underlying SiO2 layer, thus enabling a selective removal of the SiO2 layer using hydrofluoric acid. Then, the top PCD thin-film was separated from the substrate and formed a PCD NM. This PCD NM can be manipulated using various micro-transfer-printing techniques. Fig. 1(b)-(d) show the optical and scanning electron microscopy (SEM) images of free-standing PCD NMs after the process step (v) in Fig. 1(a). Fig. 1(e) presents transfer-printed PCD NM onto PET substrate using a micro-transfer-printing method. The free-standing nature of PCD NM allows us to access both top and bottom surfaces. Fig.2 shows a statistical distribution of grain sizes of the top (Fig. 2(a)) and bottom (Fig. 2(b)). Interestingly, the average grain size of the top and bottom sides of PCD NM were measured to be ~1.2um and 0.17um, respectively. This is due to a growth mechanism of the PCD thin-film (seed-to-crystalization), therefore, this result gives a possibility to engineer the size of the PCD grain larger. As shown in Fig.3, changes in a structural property of PCD thin-film and NM were investigated using Raman spectroscopy with the following three surfaces: (i) top surface of as-grown PCD on SiO2/Si sample, (ii) top surface of PCD NM, (iii) bottom surface of PCD NM. Strong sp3 peaks at 1332 cm-1 were obsevered from all three conditions. Noticebly, a relative intensity of carbon-boron vibrational modes at 1220 cm-1 is higher on the top surface than the bottom surface, suggesting that boron incorporation in the carbon lattice was poor in the beginning. To further investigate the doping quality in PCD NM, a transmission line method (TLM) method was employed. Total six TLM ohmic metal (Ti/Au=30nm/150nm) pads were deposited using an electron-beam evaporator. Fig.4 indicates I-V curves measured from TLM pads, showing a good linear I-V characteristic. Contact resistance and sheet resistance values were calculated from Resistance-Distance curve in Fig. 4(b), yielding 27 ohm and 37 ohm/sq, respectively. In summary, high-quality PCD NMs were successfully created and their manipulation methods were demonstrated. Various material properties of top and bottom surfaces of PCD NMs can be investigated and reveals differences in grain size, surface morphology and doping. PCD NMs can readily be implemented in various ways in electronics to improve the performance or to create new applications. For example, PCD NMs can be used to demonstrate 3D-stackable electronics, highly reliable bioelectronics, less-corrosive electrodes, heat dissipator and flexible electronics

Synthesis of Free-Standing Polycrystalline Diamond Nanomembrane

Diamond is an ultra-wide bandgap (5.47 eV) semiconductor material with exceptional physical features that enables energy-efficient high-power and high-frequency devices. We have demonstrated extremely high-power output (875 MW/cm2) [1] and high off-state breakdown voltage (3659 V) [2] of diamond MOSFETs. Recently, two-inch diameter diamond wafers were achieved on misoriented sapphire substrates [3] with a low XRC FWHM 004 of 89 arcsec and dislocation density of 1.4 ×107 cm−2, which are the lowest among heteroepitaxial diamonds. By using the misoriented substrate, the 2-inch diameter free-standing diamond wafer was successfully achieved without any cracking. An A-plane (11-20) sapphire misoriented by 7.0 o towards [0001] c-direction was used as the substrate. 1-μm-thick iridium (Ir) buffer layer was deposited on it. The diamond nucleation on the Ir buffer layer was performed using the bias-enhanced nucleation (BEN) process. Next, the diamond thick layer was grown on BEN-treated Ir buffered misoriented sapphire substrates by the microwave plasma CVD method. Each layer of the sample was characterized by XRD, AFM, and cross-sectional TEM. Crystal curvature occurred in the misorientation direction, however, no crystal curvature in the perpendicular direction was found. This is the key factor to relax the strain in the grown diamond thick layer induced by Ir/sapphire substrate and to obtain an inch-sized diamond wafer without any cracking. The misorientation angles of the diamond layer, Ir buffer layer, and sapphire substrate were measured by XRC measurements. The misorientation angles of the sapphire αsapp showed negligible variation from 6.92 to 6.94o. Surprisingly, Ir misorientation angles αIr were found to be lower than αsapp and varied from 5.69 to 5.81o. Diamond misorientation angles αDia were varied from 6.66 to 6.82o. In addition, nitrogen-doped (N-doped) diamond showed αDia of 6.25~6.38o which are lower than that of N-free diamond. This investigation showed a as αIr Dia sapp and this phenomenon could be caused by lattice relaxation during diamond, Ir growth. In conclusion, we investigated how an inch-sized diamond thick layer can be grown without any cracking on Ir/misoriented sapphire substrates. This study revealed the initial growth mechanism of the diamond on the Ir buffered misoriented sapphire and their variation of misorientation angles which determined a relation as αIr Dia sapp. [1] N. C. Saha, M. Kasu, et al., IEEE Electron Dev. Lett. 43, 777 (2022). [2] N. C. Saha, M. Kasu, et al., IEEE Electron Dev. Lett. 44, 112 (2023). [3] S. -W. Kim, M. Kasu, et al., Appl. Phys. Express 14, 115501 (2021).

Characterization of Inch-Sized Diamond Wafer Grown on Misoriented Sapphire

Polishing of polycrystalline diamond thin films with sub-nanometer roughness is demonstrated with subsequent transfer of the diamond film to other substrates. Direct growth of diamond on a substrate or device layer necessitates a barrier layer to protect the underlying substrate and the small diamond nuclei that form at the interface reduce the thermal transport of the diamond layer. However, the high surface roughness of polycrystalline diamond films also poses a challenge for integration (transfer via bonding) of such diamond films with other materials. Polycrystalline diamond-on-silicon films with large average grain size (0.7 µm) and a thickness of 2.7 µm were lapped and chemical mechanical polished (CMP). By the means of lapping and CMP, the r.m.s roughness decreased from 61 nm to 8 nm on a 40 x 40 µm2 scale, and r.m.s roughness of 0.5 nm was achieved over 1 µm2 with only small indentations (no protrusions). This low roughness paves the way for integration of the diamond film, such as thin film transfer by wafer bonding for heat dissipation of high-performance semiconductor devices. The short polishing time (2 hours) and low r.m.s. roughness shows our procedure to be successful and efficient. First, a mechanical lapping step was performed using diamond paste. The surface roughness reduction plateaued at 30 nm. However, due to the strong interface strength between the diamond layer and the silicon substrate, up to 80 kPa pressure can be used without the diamond film peeling. Additionally, the lapping step was determined to significantly save the subsequent chemical mechanical polishing time as well as the slurry usage. Scanning electron microscopy (SEM) shows that the lapping step can induce cracks on top of the grains. These cracks actually assisted their subsequent removal and were polished away during the CMP process. Scanning electron microscopy after the CMP process was used to study the surface morphology as well as diamond layer thickness before and after the polishing. We found that the surface is smooth with crevices (valleys), which is the primary causes for the roughness observed using AFM. On the plateaus between these valleys, the r.m.s. roughness reached as low as 0.5 nm, which is sufficient for wafer bonding purposes. The slurry particles and diamond debris that were deposited in the depressions during the CMP step were removed with subsequent cleaning steps. The available bonding area was around 80% percent, as determined from SEM images. The removal rate of most of the diamond layer is negligible, demonstrating that only the peak diamond protrusions were being polished and not the bulk of the diamond layer. Examples of this diamond film bonded to other substrates and the silicon substrate removed will be presented.

Chemical Mechanical Polishing of Polycrystalline Diamond Films for Integration as High Thermal Conductivity Layers

Cubic boron nitride (cBN) is a relatively less studied wide bandgap semiconductor despite its many promising mechanical, thermal, and electronic properties. We report on the electronic, structural, and optical characterization of commercial cBN crystal platelets and single crystal epitaxial films grown on silicon and diamond substrates. Temperature dependent transport measurements on the bulk substrates revealed the charge limited diode behavior of the cBN crystals. The equilibrium Fermi level of the bulk material was determined to be 0.47 eV below the conduction band and the electron conduction was identified as n-type. Unirradiated dark and amber color bulk cBN crystals displayed broad photoluminescence emission peaks centered around different wavelengths. RC series zero phonon line defect emission peaks were observed at room temperature from electron beam irradiated and oxygen ion implanted cBN crystals, making this material a promising candidate for high power microwave devices, next generation power electronics and future quantum sensing applications. Epitaxial films were grown using a plasma assisted CVD process using BF3 and Nitrogen as gas precursors on silicon substrates. Preliminary analysis of these films showed them to be a mixture of hexagonal and cubic polytypes. Photoluminescence on these films revealed a board luminescence spectrum. Additional data on these samples as well as material grown on diamond will be presented.

Electronic and Optical Characterization of Bulk and Epitaxial Single Crystals of Cubic Boron Nitride (cBN)

Introduction: We report on the first demonstration of field emission characteristics of β-Ga2O3 nano-pillar arrays fabricated using a novel damage-free etching technique. The vacuum field emission characteristics of β- Ga2O3 is interesting due to its large theoretical breakdown field strength (8 MV/cm), high mechanical and chemical stability, and resistance to surface oxidation. The current literature on vacuum field emission of Ga2O3 is limited to a single nano-pillar fabricated using FIB [2] while β- Ga2O3 nanowires made using self-catalytic bottom-up processes display low threshold fields [3]. The β-Ga2O3 nano-pillar arrays were fabricated using an in situ Ga2O3 etching technique in an ultra-high vacuum environment to realize damage free, high aspect ratio nano-pillars with atomic scale etch precision. Electrically conductive Ga2O3 nano-pillars with sub-micron widths was realized without the use of e-beam lithography. Field emission characteristics on the nano-pillars displayed an emission current of 10 nA per tip at an electric field of 400 kV/cm. The field emission characteristics were modelled using the Murphy-Good model, and the measurements were validated with a field emission orthodoxy test. Experimental: A thin SiO2 sacrificial layer was deposited on a Sn doped (1×1018 cm-3) (010) β- Ga2O3 substrate as a hard mask for the in-situ etch. Circular arrays were patterned using a conventional photolithographic tool on the SiO2 layer. A portion of the patterned SiO2 layer was etched using an inductively coupled reactive ion etcher (ICP-RIE), and the remaining SiO2 was etched in diluted buffered oxide etch to prevent plasma damage to the Ga2O3 surface during the dry etch. The Ga2O3 etch was carried out at a chamber temperature of 700 oC and a Ga flux of 5x10-7 Torr for two hours which resulted in an etch depth of ~960 nm. Formation of nano-pillar arrays, ~240 in diameter was confirmed using a scanning electron micrograph. Results: The conductive nature of the fabricated nano-pillars was confirmed using conductive atomic force microscope measurements. Field emission characteristics were measured on a wafer with three Ga2O3 nano-pillar arrays (a total of 700 nano-pillars). The measurement was carried out in a vacuum chamber with a base pressure of ~6x10-8 Pa. The nano-pillar arrays displayed an emission turn-on field ~100 kV/cm, with a field emission current of 19 nA per tip at an applied field of 385 kV/cm. The Murphy-Good plot shows a linear relationship at high electric fields ranging from 250 kV/cm to 385 kV/cm. The field enhancement factor and the ‘fc’ value at each voltage were extracted based on the slope at the 1/V value. The orthodox pass dataset was calculated to be in the range, . The measurement data of β- Ga2O3 nano-pillar arrays were found to be within the range at high electric fields ranging from 250 kV/cm to 385 kV/cm. In summary, field emission characteristics of β- Ga2O3 nano-pillar arrays were demonstrated and modelled using Murphy-Good equation alongside independent validation using the orthodoxy test. We acknowledge funding from the Air Force Office of Scientific Research (AFOSR) through Award FA9550-19-0349 (Dr. Ken Goretta and John Lungisland). J. Ludwick was supported by the Air Force Research Labs under contract No. FA8650-16-D-5408. References: [1] Appl. Phys. Lett. 119, 123503 (2021). [2] Appl. Phys. Lett. 114, 193101 (2019). [3] J. Phys. D: Appl. Phys. 42, 185409 (2009).

Demonstration of Gallium Oxide Nano-Pillar Field Emitter Arrays

High Electron Mobility Transistors (HEMTs) are widely used in telecommunication, aerospace, and military for RF and power electronic applications1. High power operation of the AlGaN/GaN HEMT is significantly limited by self-heating effects caused due to inadequate heat extraction from the localized hotspot generated near high electron mobility channel 2. Unoptimized design for heat extraction and high thermal boundary resistance at the GaN/Substrate interface are the primary causes of poor heat extraction 3. Integration of diamond heat spreaders with high thermal conductivity has shown promising results in the thermal performance of the device4. However, several factors like GaN/Diamond thermal boundary resistance (TBR), optimal distance from the hotspot, and heat spreader configuration can lead to the sub-optimal thermal performance of the device. Consequently, in this work, we implement a multi-way heat extraction strategy for improving the thermal performance of the AlGaN/GaN/Diamond HEMT using a cohesive understanding of TBR and distance from hotspot to diamond heat dissipators. AlGaN/GaN HEMT with a GaN substrate (Fig 1a), is simulated to set a baseline performance, which showed a thermal resistance of ~80 K.mm/W (fig 2). Upon replacing the GaN substrate with a Single Crystalline Diamond at the bottom of the device (fig 1b), its thermal resistance reduced by ~13 times. Despite of remarkable performance improvements, the device still suffers at high power density due to low thermal conductivity of GaN layer and high TBR at GaN/SCD interface. Device with SCD at bottom operating at 40W/mm is simulated for varying values of GaN thickness (50 -2000 nm) and GaN/SCD TBR values (3.1-20 m2K/GW). Simulation output showed reducing GaN thickness provides a better heat extraction from the bottom of the device, however, only up to an optimum thickness, going thinner leads to higher device temperature (fig 3a). The optimum thickness has a positive correlation with GaN/SCD TBR, i.e., as the TBR value increases the GaN layer optimal thickness also increases. For very thin GaN layer, a steep increase of ~ 200K is recorded near the hotspot in the Lateral temperature profile of the device (Fig 3b), going from the edge of the device (~500 K) towards the hotspot (~700 K). This demonstrates as the thickness reduces heat in unable to spread in the GaN layer before reaching the thermal interface and increases the device temperature. Owing to 500 K temperature at the side edge, further enhancements to the device are made by adding Poly-Crystalline Diamond (PCD) side walls at the edge of the device (Fig 1c) along with SCD at the bottom. The device is simulated for the same GaN layer thicknesses and TBR values (Fig 4a). For the optimized value of GaN layer (200 nm) and lowest TBR (3.1 m2K/GW) a significant drop of ~ 150 K is observed in the device temperature due to 3-way heat extraction. Lateral temperature profile (fig 4b) recorded ~330 K at GaN/PCD-sidewall interface and ~550 K at the hotspot which still showed a steep rise of ~200K, which illustrates that, lateral thermal resistance of GaN layer limits maximum heat extraction plausible from the edge of the device. Therefore, to extract heat from the hotspot region, an additional PCD layer with associated interface TBR layer is added on top of the device. The additional heat extraction path led to a temperature reduction of 70 K. Consequently, using side, top, and bottom heat extraction pathways and optimization of GaN layer in correlation with TBR, an AlGaN/GaN HEMT operating at a power density of 40W/mm are simulated with temperature ~470-500 K. [1] Fletcher, A. Superlattices and Microstructures vol. 109 519–537 (2017). [2] Gaska, R. et al. IEEE ELECTRON DEVICE LETTERS vol. 18 (1997) [3] Chen, G. PhD. et. al. Annual review of heat transfer. Volume 18 [4] Jessen, G. H. et al. IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC 271–274 (2006)

Understanding of Multi-Way Heat Extraction Using Peripheral Diamond in AlGaN/GaN HEMT by Electrothermal Simulations

Gallium nitride (GaN) MOSCAPs and MOSFETs are often investigated for high-power applications ranging from electric vehicles to photovoltaic invertors and smart electric grids. The specific material properties of GaN, including its wide bandgap, higher obtainable breakdown voltages, and higher electron mobilities, enable novel advantages not attainable using traditional silicon power devices. Among the many challenges reported for vertical GaN MOSFETs, optimization of the semiconductor/dielectric interface is crucial to improve important parameters such as threshold voltage, leakage currents, and interface trap densities (DIT). Previous work on GaAs has shown the importance of GaxOy mitigation through sequenced TMA purging for improved interfaces but has not elaborated on the impact of this on electrical output characteristics. For GaN, to date little work has been published that analyzes the impact of minimized interfacial GaxOy from optimized ALD techniques and its effect on electrical performance in MOS devices. Minimizing GaxOy formation at the semiconductor-dielectric interface is necessary to obtain optimal performance in GaN MOS structures. The fundamental understanding of the impact of improved oxide deposition techniques for GaN MOSFET gates is critical to accurately describe device performance. Relative improvements to dielectric leakage, DIT distributions, and capacitance-voltage (C-V) trends may be analyzed to understand how each is affected through the elimination of native oxide concentrations at the interface of GaN MOSFET gates. This study analyzes changes in electrical performance of Al2O3 dielectrics fabricated using atomic layer deposition (ALD) techniques on GaN epilayers grown on bulk GaN substrates (GaN-on-GaN). Traditional ALD deposition techniques for aluminum oxide (Al2O3) utilize reactions of trimethyl aluminum (TMA) and water to form dielectric films on various substrates. Previous studies have shown that gallium oxide (GaxOy) formation on gallium arsenide (GaAs) can be alleviated by cycling TMA purges during ALD deposition to control oxidation states and mitigate Ga-O and As-O bonding. For GaN, improvements to gate interfaces of high-k dielectrics such as Al2O3 are crucial to ensure optimal switching and electrical response of complex vertical GaN MOSFETs. Leakage currents and high densities of interfacial traps have been shown to reduce device performance in previous studies. This work shows improved C-V responses of ALD Al2O3 films using quasi-static capacitance measurements. Optimized films were fabricated by the mitigation of GaxOy at the semiconductor/dielectric interface. Films grown on substrates that did not receive a TMA dose prior to the H2O precursor for ALD growth of Al2O3 films show a significantly higher amount of native oxide between the semiconductor and gate dielectric. The relative percentage of native oxide found at the interface is quantified via x-ray photoelectron spectroscopy (XPS) and shows a significant reduction following TMA purges. This improved ALD technique for Al2O3 deposition also shows a reduction of mid-gap trap states and hysteresis observed during C-V testing which further indicates improved interface quality and electrical response of the tested devices. Relative improvement to film quality is dependent upon improved gate dielectric deposition techniques which diminish GaxOy concentration at the semiconductor/dielectric interface. The impact of gate interfaces on GaN MOS devices is directly linked to calculated DIT, leakage currents, and other important electrical characteristics which must be optimized on simple device structures prior to implementation in complex architectures such as vertical GaN MOSFETs.

Improving Electrical Performance of GaN-on-GaN MOS Devices Via Optimized Atomic Layer Deposition of Al2O3 Gate Dielectrics

Wide bandgap GaN holds great promises for high-efficiency power conversion systems. To realize GaN power integrated circuits (ICs), peripheral logic circuits based on GaN are necessary, such as controllers, drivers, protection circuits. By using the AlGaN/GaN high electron mobility transistors (HEMTs) platform, all these components can be integrated on a single chip, dramatically reducing parasitic effects, such as gate ringing and false turn-on of power transistors. Currently, most GaN logic circuits still rely on only n-channel devices. This is because it is challenging to realize high-performance GaN p-channel devices due to much lower hole mobilities and sheet carrier density. Recently, multi-channel heterostructure is proposed to address the tradeoff between carrier mobility and density. But there are still few reports on GaN multi-channel p-type devices partly due to the difficulty in buried p-GaN activation, unknown doping concentration and thickness of the inserted p-GaN layers, and the acceptor-holes separation process. In this work, we perform the design, modeling and fabrication of GaN-based vertically stacked 2DHG (two-dimensional hole gas) multiple p-channel Schottky barrier diodes (SBDs). The schematic of cross-section of an SBD with 5 2DHG-channels is shown in Fig. 1(a), and the energy band structure from the cutline is shown in Fig. 1(b). The device epilayers were grown by metal-organic chemical vapor deposition (MOCVD) on a sapphire substrate, consisting of a thick GaN buffer layer, a 300 nm UID-GaN layer, and multiple layers for p-channels that are composed of a 40 nm p+-GaN layer, a 20 nm UID-GaN layer, and a 15 nm Al0.2Ga0.8N layer. In order to effectively activate the buried p-GaN layers, trenches with different geometric patterns between the anode and cathode were etched by 400 nm of depth. The devices were then annealed at 800 °C for 1 hour to break the Mg-H bond and allowed the [H] to diffuse to the ambient through the etched sidewall. Moreover, these trenches are also geometrically designed as edge terminations that can eliminate high electric field crowding at reverse bias, which is necessary due to the vulnerability of the etched trenches, as shown in Fig. 2. Finally, the two electrodes and passivation layer were deposited on top of the devices. The distance between the anode and the cathode is from 15 um to 25 um. For the simulation, the impacts of doping concentration and thickness of p-GaN layers and the thickness of UID-GaN layers of the multi-channel heterostructure will be comprehensively investigated. And the ionization energy of [Mg] in GaN was set to be 300 mV. For the forward performance, as shown in Fig. 3(a), the ON-current densities at an anode voltage of －3.5 V for the SBDs with 1, 3, and 5 p-channels were extracted as 0.12, 0.26, and 0.365 mA/mm, respectively. With the thickness of each UID-GaN between p-GaN and AlGaN increasing from 2 to 5, 10, and 20 nm, as shown in Fig. 3(b), the ON-current is also increased from 0.24 to 0.265, 0.3, and 0.365 mA/mm. For the fabrication, as shown in Fig. 4(a) and 4(b), the SBD with 1 2DHG channel and 3 2DEG channels with different doping concentration in p-GaN layers have been fabricated. Compared with the SBD with 1 channel, the SBD with 3 channels and higher concentrations of doping in p-GaN layers has larger current. The performance of these devices needs to be further optimized during the following work. These results can provide critical references for the future development of GaN multiple p-channel devices such as multiple p-channel diodes and FETs for integrated power and logic circuits.

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