United States

Ill-Nitride light emitting diodes have been successfully adopted in visible display and illumination applications, and are very promising for ultra-violet wavelength applications. Tunnel junctions can provide several significant advantages for operation of both visible (for multiple active region LEDs) and UV LEDs (to act as transparent spreading layers). Recent work on tunnel junctions have demonstrated excellent characteristics for both GaN, as well as ultra-wide bandgap AlGaN. Although tunnel junctions (TJs) have been demonstrated with excellent electrical efficiency, and low voltage drop, especially for GaN-based LEDs, the absorption introduced by them has not been well-understood. Design of tunnel junctions for low voltage drop often requires the use of ultra-thin layers of lower bandgap material (such as InGaN) which could have substantial absorption at emission wavelengths. Previously used methods to calculate tunnel junction absorption losses, such as ray tracing and finite-difference time-domain FDTD [1] do not take into account photon recycling in the TJ. In this work we propose a theoretical model that can provide an intuitive understanding of the impact of photon recycling on the optical absorption losses in tunnel junctionbased LEDs. The proposed model is derived using a 1-dimensional N-cascaded GaN LED structure. The top metal contact is considered as a perfect reflector, and the output optical power is collected at the bottom side. GaN layers are assumed to be transparent, while any power absorbed by the TJ is recycled by generating an electron-hole pair (EHP) that is injected back to the active region to recombine there. The efficiency, n , by which the generated EHPs produce new photons in the active region is assumed to be the mathematical product of the IQE and the injection efficiency. The proposed closed form model takes into account the infinitely repeated photon recycling process. The model enables an estimate of the normalized light extraction efficiency, and can be compared with estimates from simple ray tracing model single and cascaded multiple active region TJ LEDs. It is shown that as the number of TJs increases and/or its absorption increases, the recycled power increases. Consequently, while ray tracing models would predict significant absorption losses, taking into account photon recycling shows that the effective loss is significantly lower. The model can also describe the impact of the internal quantum efficiency on the effective light extraction efficiency. For InGaN polarization engineered TJs, a comparison between the two models at various Indium compositions and thicknesses shows that for Ng 94F8q 76 N TJ LED, ray tracing model predicts absorption losses that are significantly higher. For example, for 3 nm 24% In-content tunnel junction, the ray tracing model predicts total absorption loss of 7.95%, whereas the loss including the photon recycling is only 2.94%. In summary, our work shows that absorption effects in tunnel junctions can be significantly overestimated if photon recycling is not taken into account. The work presented enables rational design of tunnel-junction based LEDs with accurate estimation of absorption losses. References: [1] L. and C. M. and W. C. Lalau Keraly C. and Kuritzky, “Light Extraction Efficiency Part A. Ray Tracing for Light Extraction Efficiency (LEE) Modeling in Nitride LEDs,” in III-Nitride Based Light Emitting Diodes and Applications, J. and A. H. and M. H. Seong Tae-Yeon and Han, Ed. Dordrecht: Springer Netherlands, 2013, pp. 231-269. doi: 10.1007/978-94-007-5863-6_9.

EMC 2022

Impact of Photon Recycling on Absorption Losses in Tunnel Junction-Based III-Nitride LEDs

extraction efficiency

gan led

tunnel junction


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For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Given the ongoing global health concerns associated with COVID-19 (Coronavirus), the DRC leadership has decided to hold the 2021 Device Research Conference in a virtual (online) format. This follows an enormously successful 2020 DRC held virtually, in which we had record attendance and worldwide participation of more than 875 attendees from 33 countries.

The 2021 Conference will feature:

* Informative, timely short courses in rapidly developing fields
* Oral and poster presentations on electronic/photonic device experiments and simulations
* Plenary and invited presentations given by worldwide leaders
* Evening “rump” session
* Strong student participation and Student Paper Awards

DRC is held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 23-25. As has happened in person in past years, in 2021, the virtual DRC and EMC sessions on the shared day, Wednesday, June 23, will be open to all attendees from both conferences. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences. For information on the 63rd Electronic Materials Conference, please visit the [EMC 2021 website.](https://www.mrs.org/63rd-emc/)

2021 DRC individual presentation videos will become available in Underline at the end of each technical session. A recording of each full live session with Q&A will be posted later during the conference. To facilitate re-viewing of recorded talks and sessions, the DRC Underline site will remain open through 11:59pm (US EDT) on July 7th. DRC Conference registration will remain open at www.mrs.org/drc-2021/registration through June 30th.

Thank you for joining us at the 2021 Device Research Conference!

**General Chair**
<br>Zhihong Chen, Purdue University

**Technical Program Chair**
<br>Becky (R.L.) Peterson, University of Michigan

**Technical Program Vice-Chair**
<br>Gregg Jessen, BAE Systems

You can register for the 79th Device Research Conference with the following link. https://www.mrs.org/drc-2021

DRC 2021

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

technical paper

After two years of virtual conferences, we're excited to host EMC 2022 in person at The Ohio State University in Columbus, Ohio. In addition to cutting-edge technical presentations given in multiple parallel sessions, opportunities to network with colleagues will be present throughout the conference. The size and format of the meeting makes networking easy, whether you have been coming to the conference for many years or are a first-time attendee.

EMC is coordinated with the Device Research Conference (DRC), which will be held the same week, from June 26-29. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

For information on the 80th Device Research Conference, please visit the DRC 2022 website.



The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

Degradation of materials under harsh, high-temperature conditions is one of the grand challenges of high-performance energy conversion. Current approaches make use of refractory materials that do not possess ideal properties but are resistant to decomposition by heat. To suppress undesired thermal transport, multiple refractory materials are shaped and arranged with varying degrees of complexity, ranging from multilayers to plasmonic arrays and 3D photonic crystals. Ultimately these structures progress toward more thermodynamically favorable configurations and result in intermixing, reaction or new phase formation, and coarsening. This severely limits their performance in extreme conditions. Here, we introduce the concept of using immiscible refractory oxides with high crystallinity as building blocks of functional ultrahigh-temperature materials. We demonstrate epitaxial oxide heterostructures made from perovskite BaZry gHfy 593 (BZHO) and rocksalt MgO as a photonic crystal (PhC) that can suppress undesired thermal emission at a desired cutoff wavelength. The PhC is implemented as surface filter to suppress mid-infrared thermal emission from the best intrinsic, spectrally selective emitter operating at 1350°C in air. The heterostructure exhibits coherent atomic registry that retains clearly separated refractive index mismatched layers without interface coarsening, interdiffusion, phase change, or decomposition up to at least 1100°C in dry air. The use of dissimilar crystal structures, with low lattice and thermal expansion mismatch, allows for high crystallinity superlattices with interlayer immiscibility at high temperatures. The understanding gained from this study can be used to develop thermal barrier coatings and selective emitters that are resistant to instabilities in air. Beyond BZHO/MgO, we computationally identify ~10° potential oxide pairings that fit our design criteria, demonstrating the vast potential of this approach.

Control of Thermal Transport at Ultrahigh Temperatures by Immiscible Oxide Heterostructures

Among compound semiconductors, Silicon Carbide (SiC) is useful especially in the high voltage, fast switching applications. Like with all technology areas, as SiC DMOSFET technology matures in terms of performance, questions of reliability and failure take on a more central role [1]. The short circuit (SC) capability addresses a key failure mechanism in these devices. The current and the lattice temperature of the device increase tremendously with the voltage stress leading to the device burning out. Among various reasons reported for this, the conducting paths created due to the melting of contacts (Aluminum) may be considered the most important factor [1]. In this work, we investigate the effect of possible process-induced variability on SC capability by 2-D simulation. Device and Simulation Setup A generic 1200 V vertical SiC DMOSFET structure, shown in Fig. 1, is simulated in a non-isothermal environment of the TCAD platform to study the short circuit capability of the device. Thus, we have used the thermodynamic model in addition to the usual drift-diffusion for electrons and holes. The parameters for bulk and interface mobility, its degradation with temperature, and thermal parameters such as thermal conductivity and specific heat capacity have been taken from the experimental literature. The acceptor type interface trap (Qa = 1.5x10 “cm at EG EE = 0.18 eV) and oxide fixed charge density 2x10 cm ~ are defined at SIC/SIO, for the simulation. The device is normally off type, and the important parameters are tabulated in Table 1. Results We consider the variability arising from two possible processes for self-aligned channel formation. The first, illustrated in Fig. 2.a, arises from the dry etch process used to form an oxide spacer which follows the p-well implant defined by the oxide hard mask. The spacer then acts as a hard mask during the n* source region implant so as to define the channel (additive). The distance between the two p-well, in this case, is fixed. Thus, channel length variability, in this case, is towards the n’-source side ('1'). The second, illustrated in Fig. 3.a, arises from a wet etch process to move back the oxide hard mask, which is used for the n*-source implant. The shortened oxide now constitutes a hard mask for the p-well implant, and thereby defines the channel (subtractive). The distance between the two n’ -source implants, in this case, is fixed. The channel length variability, in this case, is therefore from the JFET region side (‘2’). The total cell pitch remains constant in both cases. We consider both a decrease and an increase of channel length from each side. Fig. 2.6 shows the variability of type '1', while Fig. 3.6 shows the variability of type '2'. The effect of these variability types on the SC capability is different and depends on the effective channel length, which here ranges from 0.3 to 0.7 um. For type '1', the effective channel length increases and decreases with n’ -source, and most of the other device parameters are not affected as shown in Table 1. For type '2', the varied channel length is effectively changing the JFET dimensions. The combined effect is more pronounced which can be observed from the resulting SC curves. The SC capability of the device worsens with a decrease in channel length since that leads to higher currents. The results indicate that the additive method of fabrication is preferable for the SiC-based DMOSFET for reproducible SC performance. Acknowledgement This work was supported by the IIT Bombay-Ohio State Frontier Science and Engineering Research Center under “Towards the rugged SiC technology for electric transportation” project. Reference 1. Hema Lata Rao Maddi, Susanna Yu, Shengnan Zhu, Tian-shi Liu, Limeng Shi, Minseok Kang, Diang Xing, Suvendu Nayak, Marvin H. White, and Anant K. Agarwal, “The road to a robust and affordable SiC power MOSFET technology, “Energies, vol. 14, no. 24, pp. 8283, Dec 2021.

Process-Induced Variability of SiC DMOSFET Short Circuit Capability

The LiNiy 5Mn, 504 (LNMO) spinel cathode has been extensively researched as a promising candidate for next-generation Li-ion batteries owing to its high operating voltage (~ 4.7 Vs Lid and high specific energy (650 Wh/kg). In addition to this, its cobalt-free composition and excellent rate capability due to threedimensional Li? diffusion makes it particularly attractive for a wide range of applications. However, the high operating voltage in full-cells (LNMO/Graphite) triggers unwanted parasitic reactions at the electrode/electrolyte interface which lead to active Li* consumption and consequent capacity fading. Elemental substitution of Ni/Mn is a very actively pursued strategy to alleviate the capacity fading. In particular, Tisubstitution for Mn in LiNiy Mn, 5x Og (LNMTO) has improved the full-cell performances as evidenced by (i) higher capacity retention and Coulombic efficiency and (ii) lower oxidative reaction and self-discharge rates. The primary improvement mechanism of the Ti-substitution in LNMTO is a formation of Ti-enriched passivation layer at the expense of initial Mn-dissolution at the cathode- electrolyte interface (CEI). Once generating the passivation layer, further Mn-dissolution became suppressed. Despite these results, carbon conductor (Super P) inside cathode still actively oxidizes the electrolyte due to its good electrical conductivity and large surface areas. In this regard, we adopted advanced binders to passivate the carbon conductors for the LNMTO cathodes. Polyvinylidene fluoride (PVdF) has been used as the binder in cathodes due to its electrochemical stability. However, PVdF does not offer the effective passivation of carbon conductors, while suffering from mediocre adhesion strength and raising environmental concerns by using N-Methyl-2-pyrrolidone (NMP), a toxic organic solvent. Studies have shown that advanced aqueous binder chemistries can be used to create an effective passivating layer at the cathodeelectrolyte interface, improve adhesion strength and eliminate the use of toxic organic solvents. Among them, lithium polyacrylate (LIPAA) has demonstrated positive multifunctions such as proton scavenging, donating Li? and effective passivation of both carbon and active material particles. Our full-cell testing data showed that the LiIPAA binder in LNMTO cathodes delivered an improved cycle life and a lower cell impedance compared to those of PVdF binder in LNMTO cathodes. To better understand the characteristics of the CEI passivation on the LiPAA and LNMTO cathodes, we will discuss about the various surface analyses of the fresh and aged electrodes using XPS, Raman, and HR-TEM.

Strategy to Passivate High-Voltage Spinel Cathode-Electrolyte Interfaces (CEI)

Bio-inspired devices and systems have effectively showed its potential in the current era of neuromorphic chips. Moreover, it has also depicted the capability to bridge the gap between natural and artificial intelligence. It must be highlighted that imitating the functionalities of a brain paves the way for smart computing with an intent to solve complex problems. In this context, the spiking neural networks (SNNs) have captured a lot of attention as it mimics the processing of information with minimum energy consumption and faster inference. Note that, the SNNs tend to convert the external stimuli into corresponding spike trains by exploiting some afferent neurons. Here, we have designed and fabricated an optoelectronic integrated circuit comprising of 21 memtransistors based on monolayer MoS., for spike-timing dependent photo encoding. In addition to this, we have demonstrated that the different illumination intensities can be efficiently encoded into spike trains, where the time to the first spike determines the strength of the visual stimuli, i.e., higher illumination intensity generates earlier spikes and vice versa. Furthermore, the non-volatile storage and electrical programming capability of the photo sensitive memtransistors enables the encoder for photo encoding with controlled adaptivity that allows accelerated spike trains under low light condition and delayed spike trains under higher illumination intensities, respectively. Therefore, it can be inferred that our demonstration of the spike-timing based photo encoder exploiting the 2D memtransistors can be transformative for cutting-edge neuromorphic applications.

Spike-Timing Based Adaptive Photo Encoder Considering Monolayer MoS2 Based Memtransistors

Organic electrochemical transistors (OECTs) have attracted great attention since their discovery in 1984 due to their flexibility and biocompatibility. Although an intense focus has been put on the design of new organic semiconductors, fewer efforts are directed towards the development of optimized electrolytes. However, the electrolyte is an integral part of OECTs and strongly influences the transient responses of these devices. Also, best performing OECTs currently use liquid electrolytes, but there is a growing need for solid electrolytes, as they can be easily integrated into wearable devices. Here, we demonstrate that ionic liquid crystal elastomers can be used as solid electrolytes of flexible, substrate-free organic electrochemical transistors. We introduce the alignment of the director of the liquid crystal elastomers as a new parameter to tune and improve both steady state and transient responses. The normalized maximum transconductance 94/ of the most sensitive iLCE, was found to be the highest (7 Sm_ ) among all solid state-based OECTs. [1] Acknowledgements: This research was supported by the National Science Foundation under grant DMR-1904167 and ECCS 1750011. References: [1] C. P. H. Rajapaksha, P. R. Paudel et al., Applied Physics Reviews, In press (2022).

Substrate-Free Organic Electrochemical Transistors Based on Ionic Liquid Crystal Elastomer

Photoluminescence (PL) has been under intense scrutiny in an attempt to define the mechanisms that generate the emissions in gallium oxide (Ga,0.). In general, PL spectra is used to characterize the defects leading to radiative recombination processes within a specific material. In this regard, the PL spectra for B-Ga,0, has generally been deconvoluted in three emission peaks: UV, blue, and green. However, peak shapes from any point defect are expected to require more than a single Gaussian for a complex crystal structure like B-Ga,0., possibly having an asymmetric shape and requiring a more complex model, which takes into consideration the vibrational broadening of the PL spectrum due to electron-phonon coupling. The sum of many phonon replicas makes it challenging to fit the spectra uniquely. Adding energy level broadening from disorder or extended defects makes deconvolution of the B-Ga 793 PL spectra even more difficult. As such, there is little chance of being able to spectroscopically discern different types of defects in B-Ga,0, from luminescence as any defect considered can result in a very wide luminescence band, even near 0 Kelvin. This has resulted in an intense debate in defining the defects and phenomenological explanations of electronic processes that cause these particular emissions. In these debates, point defects have been the only explored and discussed potential source for the visible PL emission in B-Ga,0.. But, as far as can be determined, no previous works in the literature have discussed whether extended defects affect PL. Here, a systematic PL study on three series of B-Ga,0, /aluminum gallium oxide films and bulk single crystals is performed. The first series includes three film samples with varying Si-doping: UID (~10 ~cm_~),~10 cm, and ~10'8 om”, All samples in the series are (010) oriented Si-doped B-Ga,0, film grown on Fe-doped B-Ga,0.. The second series contains three samples and compares (-201) B-Ga,0.. This series includes a bulk crystal of (-201) UID B-Ga,0., a (-201) UID B-Ga,0, film grown on Fe-doped B-Ga,0., and a (-201) UID B-Ga,0, film grown on sapphire. The last series compares (010) oriented (Al Ga, _)903 films, i.e., AGO of varying Al concentrations (0%, 10%, and 25%), grown on Fe-doped B-Ga,,O.,,. These are compared to a (100) oriented bulk 10% AGO (B-Alp Ga 2-3 . O,,) crystal. A second part of the series compares (-201) oriented 0%, 2%, 10%, and 28% AGO films grown on 3 sapphire. The Si-doped series yields homogeneous crystalline films with a low density of extended defects [1] and a dominant UV emission in PL. In the (-201) series, the bulk (-201) B-Ga,0, sample also shows a dominant UV emission. On the other hand, Heteroepitaxial and homoepitaxial (-201) B-Ga,0, films show consistent PL features with dominant blue emission. The (-201) films’ poor quality [2, 3] is likely the reason for this shift in the dominant emission, as observed when comparing UID films grown on (010) and (-201) bulk B-Ga,0, crystals with comparable growth conditions. The AGO series shows consistent blue centered PL with no UV emission for both homoepitaxial and heteroepitaxial AGO samples. The AGO films show extended defects throughout a poor-quality film revealed using transmission electron microscopy (TEM) on the 25% AGO grown on (010) bulk B-Ga,0, crystal. Lastly, representative samples chosen from all three series were compared and it is shown that extended defects have an essential role in the PL emission of B-Ga,0., and AGO films. Homogeneous films with no extended defects or stacking faults and bulk crystals will yield a UV dominant PL emission. Samples of poor film quality that have stacking faults and extended defects will have a dominant blue PL emission. 1.8 References: [1] Rafique, S., et al., Appl. Phys. Lett. 108, 182105 (2016). [2] Ghadbeigi, L., et al., Journal of Elec Materi. 50, 2990-2998 (2021). [3] Eisner, B. A., et al., J. Appl. Phys. 128, 195703 (2020).

Effect of Extended Defects on Photoluminescence of Gallium Oxide and Aluminum Gallium Oxide Epitaxial Films

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.

Interface Trap Density Characterization of ALD Gate Dielectrics for GaN Power MOSFETs

Digital neural networks (NNs) and the availability of large training datasets have allowed for rapid progress in the performance of machine-based tasks for a wide range of applications including image analysis, sound recognition, and natural language translation. The enhanced capability has, however, come at a computational cost as increased complexity and accuracy have necessitated the need for ever larger deep neural networks (DNNs). One alternative to DNNs is the use of optical processors that have the advantages of ultra-fast processing times and low energy costs. These systems can be employed as stand-alone processors or as front-end accelerators for digital systems. In either case, optical systems are most impactful when used for the linear matrix-vector multiplications that comprise the convolution operations in DNNs as these are often the most computationally burdensome components typically comprising more than 90% of the required floating-point operations (FLOPs) in popular CNNs. In the case of image analysis, free-space approaches are attractive as spatial multiplexing can be readily achieved as well as the fact that an optical front-end can potentially be integrated directly with an imaging system. The most traditional approach to free-space based optical image processing is the use of 4f optical correlators where spatial filters, either passive or dynamic, are placed in the Fourier plane of a 2-lens optical system. Recorded spatial features are then fed to a lightweight digital NN back-end for classification. An alternative approach is the use of diffractive neural networks which utilize cascaded diffractive elements as convolutional layers. Image classification is realized through redistribution of optical energy on the detector plane requiring minimal digital processing. The tradeoff is the need for several diffractive layers as well as coherent illumination, precluding use with ambient lighting. While these approaches have shown benefits in terms of processing speed and energy consumption, they necessitate enlarged imaging systems. Furthermore, none of these approaches utilize the additional information channels, such as polarization, that are available when utilizing an optical front-end. Here, we demonstrate the use of meta-optic based optical accelerators that serve as the convolutional front-end for a hybrid image classification system. Spatial multiplexing is achieved by using a multi-channel metalens for image duplication and a metasurface-based convolutional layer. This system has the advantage of being compact while the use of metasurfaces allows for additional information channels, in this case, polarization, to be accessed enabling both image and polarization-based classification. The hybrid network utilizes end-to-end design such that the optical and digital components are co-optimized while also incorporating statistical noise resulting in a robust classification network. We experimentally demonstrate the classification of the MNIST dataset with an accuracy of 92% as well as 94% accurate classification of polarized MNIST digits. Due to the compact footprint, ease of integration with conventional imaging systems, and ability to access additional information channels, this type of system could find uses in high-dimensional imaging, information security, and machine vision.

Meta-Optic Accelerators for Object Classifiers

It was both theoretically and experimentally proved that the growth of In Ga 4-xN quantum wells (QWs) on In Ga,_ N underlayer (x > y) would significantly improve the light emitting diodes (LEDs) performance, attributing to the reduction of non-radiative recombination centers, the decline of the internal electrostatic field, and the improvement of indium composition uniformity in QWs. Moreover, the reduced lattice mismatch between QWs and underlayer greatly suppresses composition pulling effect, which improves indium incorporation rate grown at the same temperature, resulting in In-rich InGaN with highly crystalline. However, to serve as templates for red emission QWs, a thicker InGaN pseudo-substrate with closer indium mole fraction to QWs grown beyond the critical layer thickness is desired. In this work, we present an approach to achieve a sub-micron size InGaN underlayer with high to 30 % indium composition, while the thickness is around 90 nm, far exceeding the critical layer thickness of such In-rich InGaN layer on planar c-plane GaN (reported less than 5 nm). The InGaN platelet is demonstrated by selective area growth (SAG) on arrays of GaN seed from circle openings with a diameter of 400 nm ina SiN, mask. To our best knowledge, SAG of InGaN results in random nucleation and uneven shape due to the low diffusion length of gallium precursor at relatively low growth temperature. It was reported that the selectivity of InGaN can be enhanced by introducing pyramid shaped GaN seed first, resulting in InGaN pyramid. However, the local indium composition fluctuation on the semipolar facet of the InGaN pyramid hinders pure red emission of QWs with small full width at half maximum (FWHM). In this work, planar hexagonal shape of GaN seed was introduced first before SAG of InGaN, leading to the formation of uniform InGaN platelets with c-plane domain morphology. The optical properties of the InGaN platelets were characterized by photoluminescence (PL, excited by a He-Cd laser of 325 nm, 15 mW, room-temperature), showing PL peaks around 530 nm with FWHM of 141 meV, suggesting around 30 % indium incorporated. AFM scan of the top c-plane surface of the InGaN platelet indicates an atomically flat surface without v-pits or trench defects while the thickness is over 90 nm. Cross-sectional TEM characterization of InGaN platelet suggests homogenous crystalline and shape interface between InGaN and GaN seed. According to localized EDX line measurements recorded with the same area, the InGaN platelet shows indium composition almost linearly increased from InGaN/GaN interface to c-plane surface. Detailed line profiles show indium composition of 25 % to 30 % at the top surface and 15 % to 20 % at InNGaN/GaN interface. Such high indium-content InGaN platelets are competitive candidates for the development of high-quality yellow-to-red emission InGaN micro-LED, by increasing the indium incorporation rate and reducing the lattice mismatch for later Inrich quantum wells.

High In-Content InGaN Platelets as Underlayer for Light-Emitting Diodes Toward Long Wavelength Application

This abstract explores the possibility of employing metal additive microfabrication of system in package (SiP) with inbuilt heat sinks and leadframe consisting of multiple pads for QFN packaging. The SiPs were fabricated using 17-4Ph stainless steel powder employing a relatively less expensive DMLS system. The use of affordable metal additive manufacturing systems is considered by the authors to encourage further research on its applicability towards heterogenous integration in the semiconductor industries. The International Technology Roadmap for Semiconductors (IRTD) 2012 emphasized on the importance of integration of system on chip (SoC) and SiP. DMLS is one possibility for such heterogenous integration due to the possibility of customization as the parts are directly fabricated from a CAD file. DMLS has been considered superior to its plastic or resin-based counterparts in applications where conductive parts with better accuracy and strength are required. All these features make DMLS parts, a possible option for the fabrication of SiP with few functionalities like heat sinks and connectivity. 3D packaging and heat extraction for die is one of the grand challenges of International Roadmap for Devices and Systems (IRDS). In this abstract, different QFN leadframes with and without cooling systems are presented. The original leadframe design with only the pads forms a comparison reference for the remaining three systems. The three systems are: QFN leadframe with microchannel, inlet, and outlet for fluid flow, QFN leadframe with arrays of fins below the die location, and a QFN leadframe with fins along with additional inlet and outlet for optional fluid flow. Figure 1 shows the CAD top views of all four proposed package system. Each package system can hold a 1cm by 1cm semiconductor die for testing purposes. The microchannels are 500um square channels whereas the fins are 1000um in diameter. The affordability comes with the trade-off of resolution and the present DMLS system can faithfully produce the mentioned dimensions with compatible features for the channels and fins. The first step towards the fabrication of the packages is the CAD design and simulation. The CAD design was then fed to the metal 3D printer, which then sliced the model and created 3D laser part. The fabrication proceeds by melting and fusing a 30um layer of powder, repeating the process, creating layers on top of layers, and fusing them together until the final 3D part is built as per the CAD file. EDM wire cutting or grinding of previously created support structure could be used to separate the parts from the build plate. Figure 2 shows the steps involved in fabrication. On each separate parts, 1cm by 1cm semiconductor dies (all same) are carefully placed. Wire bonding will be used to connect the via to the leadframe pads and inlets/outlets will be extended. The whole system will then be covered with epoxy and left to cure. The final step will be to grind away the back end of the cured part to remove support metal plate on the bottom of the packaging parts as shown in Figure 3. Figure 4 shows the separated parts with a spot for semiconductor die to be affixed and various other sub-parts. Figure 5 shows the water (colored for visibility) filled leadframe with microchannel, and the other one with fins, inlet, and outlet is shown in Figure 6. Figure 7 shows the preliminary infra-red image of all four devices heated to 40°C and left to cool down. The devices were in the same order as Figure 4. As per the theoretical idea, fins with channels performs the best followed by the one with microchannel, and the one with only fins based on the time required for them to cool down (a-f in Figure 4). The preliminary result appears promising and the material characterization along with testing is in process. Figure 8 and 9 shows the SEM characterization of build device compared to the design. The variation from the design is very small.

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