United States

Among compound semiconductors, Silicon Carbide (SiC) is useful especially in the high voltage, fast switching applications. Like with all technology areas, as SiC DMOSFET technology matures in terms of performance, questions of reliability and failure take on a more central role [1]. The short circuit (SC) capability addresses a key failure mechanism in these devices. The current and the lattice temperature of the device increase tremendously with the voltage stress leading to the device burning out. Among various reasons reported for this, the conducting paths created due to the melting of contacts (Aluminum) may be considered the most important factor [1]. In this work, we investigate the effect of possible process-induced variability on SC capability by 2-D simulation. Device and Simulation Setup A generic 1200 V vertical SiC DMOSFET structure, shown in Fig. 1, is simulated in a non-isothermal environment of the TCAD platform to study the short circuit capability of the device. Thus, we have used the thermodynamic model in addition to the usual drift-diffusion for electrons and holes. The parameters for bulk and interface mobility, its degradation with temperature, and thermal parameters such as thermal conductivity and specific heat capacity have been taken from the experimental literature. The acceptor type interface trap (Qa = 1.5x10 “cm at EG EE = 0.18 eV) and oxide fixed charge density 2x10 cm ~ are defined at SIC/SIO, for the simulation. The device is normally off type, and the important parameters are tabulated in Table 1. Results We consider the variability arising from two possible processes for self-aligned channel formation. The first, illustrated in Fig. 2.a, arises from the dry etch process used to form an oxide spacer which follows the p-well implant defined by the oxide hard mask. The spacer then acts as a hard mask during the n* source region implant so as to define the channel (additive). The distance between the two p-well, in this case, is fixed. Thus, channel length variability, in this case, is towards the n’-source side (&#39;1&#39;). The second, illustrated in Fig. 3.a, arises from a wet etch process to move back the oxide hard mask, which is used for the n*-source implant. The shortened oxide now constitutes a hard mask for the p-well implant, and thereby defines the channel (subtractive). The distance between the two n’ -source implants, in this case, is fixed. The channel length variability, in this case, is therefore from the JFET region side (‘2’). The total cell pitch remains constant in both cases. We consider both a decrease and an increase of channel length from each side. Fig. 2.6 shows the variability of type &#39;1&#39;, while Fig. 3.6 shows the variability of type &#39;2&#39;. The effect of these variability types on the SC capability is different and depends on the effective channel length, which here ranges from 0.3 to 0.7 um. For type &#39;1&#39;, the effective channel length increases and decreases with n’ -source, and most of the other device parameters are not affected as shown in Table 1. For type &#39;2&#39;, the varied channel length is effectively changing the JFET dimensions. The combined effect is more pronounced which can be observed from the resulting SC curves. The SC capability of the device worsens with a decrease in channel length since that leads to higher currents. The results indicate that the additive method of fabrication is preferable for the SiC-based DMOSFET for reproducible SC performance. Acknowledgement This work was supported by the IIT Bombay-Ohio State Frontier Science and Engineering Research Center under “Towards the rugged SiC technology for electric transportation” project. Reference 1. Hema Lata Rao Maddi, Susanna Yu, Shengnan Zhu, Tian-shi Liu, Limeng Shi, Minseok Kang, Diang Xing, Suvendu Nayak, Marvin H. White, and Anant K. Agarwal, “The road to a robust and affordable SiC power MOSFET technology, “Energies, vol. 14, no. 24, pp. 8283, Dec 2021.

EMC 2022

Process-Induced Variability of SiC DMOSFET Short Circuit Capability

short circuit

mosfet

silicon carbide

After two years of virtual conferences, we're excited to host EMC 2022 in person at The Ohio State University in Columbus, Ohio. In addition to cutting-edge technical presentations given in multiple parallel sessions, opportunities to network with colleagues will be present throughout the conference. The size and format of the meeting makes networking easy, whether you have been coming to the conference for many years or are a first-time attendee.

EMC is coordinated with the Device Research Conference (DRC), which will be held the same week, from June 26-29. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

For information on the 80th Device Research Conference, please visit the DRC 2022 website.



The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

Among compound semiconductors, Silicon Carbide (SiC) is useful especially in the high voltage, fast switching applications. Like with all technology areas, as SiC DMOSFET technology matures in terms of performance, questions of reliability and failure take on a more central role [1]. The short circuit (SC) capability addresses a key failure mechanism in these devices. The current and the lattice temperature of the device increase tremendously with the voltage stress leading to the device burning out. Among various reasons reported for this, the conducting paths created due to the melting of contacts (Aluminum) may be considered the most important factor [1]. In this work, we investigate the effect of possible process-induced variability on SC capability by 2-D simulation. Device and Simulation Setup A generic 1200 V vertical SiC DMOSFET structure, shown in Fig. 1, is simulated in a non-isothermal environment of the TCAD platform to study the short circuit capability of the device. Thus, we have used the thermodynamic model in addition to the usual drift-diffusion for electrons and holes. The parameters for bulk and interface mobility, its degradation with temperature, and thermal parameters such as thermal conductivity and specific heat capacity have been taken from the experimental literature. The acceptor type interface trap (Qa = 1.5x10 “cm at EG EE = 0.18 eV) and oxide fixed charge density 2x10 cm ~ are defined at SIC/SIO, for the simulation. The device is normally off type, and the important parameters are tabulated in Table 1. Results We consider the variability arising from two possible processes for self-aligned channel formation. The first, illustrated in Fig. 2.a, arises from the dry etch process used to form an oxide spacer which follows the p-well implant defined by the oxide hard mask. The spacer then acts as a hard mask during the n* source region implant so as to define the channel (additive). The distance between the two p-well, in this case, is fixed. Thus, channel length variability, in this case, is towards the n’-source side ('1'). The second, illustrated in Fig. 3.a, arises from a wet etch process to move back the oxide hard mask, which is used for the n*-source implant. The shortened oxide now constitutes a hard mask for the p-well implant, and thereby defines the channel (subtractive). The distance between the two n’ -source implants, in this case, is fixed. The channel length variability, in this case, is therefore from the JFET region side (‘2’). The total cell pitch remains constant in both cases. We consider both a decrease and an increase of channel length from each side. Fig. 2.6 shows the variability of type '1', while Fig. 3.6 shows the variability of type '2'. The effect of these variability types on the SC capability is different and depends on the effective channel length, which here ranges from 0.3 to 0.7 um. For type '1', the effective channel length increases and decreases with n’ -source, and most of the other device parameters are not affected as shown in Table 1. For type '2', the varied channel length is effectively changing the JFET dimensions. The combined effect is more pronounced which can be observed from the resulting SC curves. The SC capability of the device worsens with a decrease in channel length since that leads to higher currents. The results indicate that the additive method of fabrication is preferable for the SiC-based DMOSFET for reproducible SC performance. Acknowledgement This work was supported by the IIT Bombay-Ohio State Frontier Science and Engineering Research Center under “Towards the rugged SiC technology for electric transportation” project. Reference 1. Hema Lata Rao Maddi, Susanna Yu, Shengnan Zhu, Tian-shi Liu, Limeng Shi, Minseok Kang, Diang Xing, Suvendu Nayak, Marvin H. White, and Anant K. Agarwal, “The road to a robust and affordable SiC power MOSFET technology, “Energies, vol. 14, no. 24, pp. 8283, Dec 2021.

technical paper

The LiNiy 5Mn, 504 (LNMO) spinel cathode has been extensively researched as a promising candidate for next-generation Li-ion batteries owing to its high operating voltage (~ 4.7 Vs Lid and high specific energy (650 Wh/kg). In addition to this, its cobalt-free composition and excellent rate capability due to threedimensional Li? diffusion makes it particularly attractive for a wide range of applications. However, the high operating voltage in full-cells (LNMO/Graphite) triggers unwanted parasitic reactions at the electrode/electrolyte interface which lead to active Li* consumption and consequent capacity fading. Elemental substitution of Ni/Mn is a very actively pursued strategy to alleviate the capacity fading. In particular, Tisubstitution for Mn in LiNiy Mn, 5x Og (LNMTO) has improved the full-cell performances as evidenced by (i) higher capacity retention and Coulombic efficiency and (ii) lower oxidative reaction and self-discharge rates. The primary improvement mechanism of the Ti-substitution in LNMTO is a formation of Ti-enriched passivation layer at the expense of initial Mn-dissolution at the cathode- electrolyte interface (CEI). Once generating the passivation layer, further Mn-dissolution became suppressed. Despite these results, carbon conductor (Super P) inside cathode still actively oxidizes the electrolyte due to its good electrical conductivity and large surface areas. In this regard, we adopted advanced binders to passivate the carbon conductors for the LNMTO cathodes. Polyvinylidene fluoride (PVdF) has been used as the binder in cathodes due to its electrochemical stability. However, PVdF does not offer the effective passivation of carbon conductors, while suffering from mediocre adhesion strength and raising environmental concerns by using N-Methyl-2-pyrrolidone (NMP), a toxic organic solvent. Studies have shown that advanced aqueous binder chemistries can be used to create an effective passivating layer at the cathodeelectrolyte interface, improve adhesion strength and eliminate the use of toxic organic solvents. Among them, lithium polyacrylate (LIPAA) has demonstrated positive multifunctions such as proton scavenging, donating Li? and effective passivation of both carbon and active material particles. Our full-cell testing data showed that the LiIPAA binder in LNMTO cathodes delivered an improved cycle life and a lower cell impedance compared to those of PVdF binder in LNMTO cathodes. To better understand the characteristics of the CEI passivation on the LiPAA and LNMTO cathodes, we will discuss about the various surface analyses of the fresh and aged electrodes using XPS, Raman, and HR-TEM.

Strategy to Passivate High-Voltage Spinel Cathode-Electrolyte Interfaces (CEI)

Bio-inspired devices and systems have effectively showed its potential in the current era of neuromorphic chips. Moreover, it has also depicted the capability to bridge the gap between natural and artificial intelligence. It must be highlighted that imitating the functionalities of a brain paves the way for smart computing with an intent to solve complex problems. In this context, the spiking neural networks (SNNs) have captured a lot of attention as it mimics the processing of information with minimum energy consumption and faster inference. Note that, the SNNs tend to convert the external stimuli into corresponding spike trains by exploiting some afferent neurons. Here, we have designed and fabricated an optoelectronic integrated circuit comprising of 21 memtransistors based on monolayer MoS., for spike-timing dependent photo encoding. In addition to this, we have demonstrated that the different illumination intensities can be efficiently encoded into spike trains, where the time to the first spike determines the strength of the visual stimuli, i.e., higher illumination intensity generates earlier spikes and vice versa. Furthermore, the non-volatile storage and electrical programming capability of the photo sensitive memtransistors enables the encoder for photo encoding with controlled adaptivity that allows accelerated spike trains under low light condition and delayed spike trains under higher illumination intensities, respectively. Therefore, it can be inferred that our demonstration of the spike-timing based photo encoder exploiting the 2D memtransistors can be transformative for cutting-edge neuromorphic applications.

Spike-Timing Based Adaptive Photo Encoder Considering Monolayer MoS2 Based Memtransistors

Organic electrochemical transistors (OECTs) have attracted great attention since their discovery in 1984 due to their flexibility and biocompatibility. Although an intense focus has been put on the design of new organic semiconductors, fewer efforts are directed towards the development of optimized electrolytes. However, the electrolyte is an integral part of OECTs and strongly influences the transient responses of these devices. Also, best performing OECTs currently use liquid electrolytes, but there is a growing need for solid electrolytes, as they can be easily integrated into wearable devices. Here, we demonstrate that ionic liquid crystal elastomers can be used as solid electrolytes of flexible, substrate-free organic electrochemical transistors. We introduce the alignment of the director of the liquid crystal elastomers as a new parameter to tune and improve both steady state and transient responses. The normalized maximum transconductance 94/ of the most sensitive iLCE, was found to be the highest (7 Sm_ ) among all solid state-based OECTs. [1] Acknowledgements: This research was supported by the National Science Foundation under grant DMR-1904167 and ECCS 1750011. References: [1] C. P. H. Rajapaksha, P. R. Paudel et al., Applied Physics Reviews, In press (2022).

Substrate-Free Organic Electrochemical Transistors Based on Ionic Liquid Crystal Elastomer

Photoluminescence (PL) has been under intense scrutiny in an attempt to define the mechanisms that generate the emissions in gallium oxide (Ga,0.). In general, PL spectra is used to characterize the defects leading to radiative recombination processes within a specific material. In this regard, the PL spectra for B-Ga,0, has generally been deconvoluted in three emission peaks: UV, blue, and green. However, peak shapes from any point defect are expected to require more than a single Gaussian for a complex crystal structure like B-Ga,0., possibly having an asymmetric shape and requiring a more complex model, which takes into consideration the vibrational broadening of the PL spectrum due to electron-phonon coupling. The sum of many phonon replicas makes it challenging to fit the spectra uniquely. Adding energy level broadening from disorder or extended defects makes deconvolution of the B-Ga 793 PL spectra even more difficult. As such, there is little chance of being able to spectroscopically discern different types of defects in B-Ga,0, from luminescence as any defect considered can result in a very wide luminescence band, even near 0 Kelvin. This has resulted in an intense debate in defining the defects and phenomenological explanations of electronic processes that cause these particular emissions. In these debates, point defects have been the only explored and discussed potential source for the visible PL emission in B-Ga,0.. But, as far as can be determined, no previous works in the literature have discussed whether extended defects affect PL. Here, a systematic PL study on three series of B-Ga,0, /aluminum gallium oxide films and bulk single crystals is performed. The first series includes three film samples with varying Si-doping: UID (~10 ~cm_~),~10 cm, and ~10'8 om”, All samples in the series are (010) oriented Si-doped B-Ga,0, film grown on Fe-doped B-Ga,0.. The second series contains three samples and compares (-201) B-Ga,0.. This series includes a bulk crystal of (-201) UID B-Ga,0., a (-201) UID B-Ga,0, film grown on Fe-doped B-Ga,0., and a (-201) UID B-Ga,0, film grown on sapphire. The last series compares (010) oriented (Al Ga, _)903 films, i.e., AGO of varying Al concentrations (0%, 10%, and 25%), grown on Fe-doped B-Ga,,O.,,. These are compared to a (100) oriented bulk 10% AGO (B-Alp Ga 2-3 . O,,) crystal. A second part of the series compares (-201) oriented 0%, 2%, 10%, and 28% AGO films grown on 3 sapphire. The Si-doped series yields homogeneous crystalline films with a low density of extended defects [1] and a dominant UV emission in PL. In the (-201) series, the bulk (-201) B-Ga,0, sample also shows a dominant UV emission. On the other hand, Heteroepitaxial and homoepitaxial (-201) B-Ga,0, films show consistent PL features with dominant blue emission. The (-201) films’ poor quality [2, 3] is likely the reason for this shift in the dominant emission, as observed when comparing UID films grown on (010) and (-201) bulk B-Ga,0, crystals with comparable growth conditions. The AGO series shows consistent blue centered PL with no UV emission for both homoepitaxial and heteroepitaxial AGO samples. The AGO films show extended defects throughout a poor-quality film revealed using transmission electron microscopy (TEM) on the 25% AGO grown on (010) bulk B-Ga,0, crystal. Lastly, representative samples chosen from all three series were compared and it is shown that extended defects have an essential role in the PL emission of B-Ga,0., and AGO films. Homogeneous films with no extended defects or stacking faults and bulk crystals will yield a UV dominant PL emission. Samples of poor film quality that have stacking faults and extended defects will have a dominant blue PL emission. 1.8 References: [1] Rafique, S., et al., Appl. Phys. Lett. 108, 182105 (2016). [2] Ghadbeigi, L., et al., Journal of Elec Materi. 50, 2990-2998 (2021). [3] Eisner, B. A., et al., J. Appl. Phys. 128, 195703 (2020).

Effect of Extended Defects on Photoluminescence of Gallium Oxide and Aluminum Gallium Oxide Epitaxial Films

This study analyzes the changes in the density of interface traps (DIT) for various atomic layer deposition (ALD) gate dielectric films on gallium nitride (GaN) devices fabricated on bulk GaN substrates. Each film type has been chosen with an optimized insulator/semiconductor interface obtained through chemical cleans or post deposition annealing (PDA). Reduction in dielectric leakage and interface traps in MOSCAP devices may be used in order to understand how these mechanisms affect more complex devices such as vertical GAN MOSFETs. GaN MOSFET and MOSCAP devices are often investigated and implemented in power systems with applications ranging from electric vehicles (EVs) to smart power grids. The unique material properties of GaN such as wide bandgap, high breakdown voltage, and high electron mobility create unique advantages over traditional silicon FETs. Vertical GAN MOSFETs are better suited for higher voltage applications due to current flow and voltage drop perpendicular to the surface while also reducing required chip area for high operating voltages. Although there are many advantages of vertical GaN devices, such an architecture presents unique challenges that must be addressed before such devices may be implemented in high power applications, such as the requirement for a native substrate and the need to improve the gate dielectric interface. The interface between the gate dielectric and the semiconductor is crucial in order to reduce threshold voltage drift, leakage current, and the density charge traps. Previous work has shown the importance of DIT reduction with chemical cleans and PDAs. Accurate calculations of the density of interface traps (DIT) are vital to fully realize device operation and reliability. The choice between surface cleans and dielectric annealing as a leakage reduction technique is dependent on the material and available processing capabilities. While PDAs may reduce the dielectric breakdown strength, they have been found to reduce gate leakage current and improve device performance for most gate dielectrics. Several methods have been proposed for DIT characterization, including the voltage dependencies of low- and highfrequency capacitance (CV), conductance (GV), and surface potential (WY). DIT may be calculated from the surface potential of the dielectric using the quasi-static capacitance and the capacitance of the chosen gate dielectric. This work uses quasi-static CV and surface potential electrical characterization of GAN MOSCAPs to determine DIT of various gate dielectric materials treated with PDAs and chemical cleans. Optimization of such films on MOSCAPs will allow for implementation into vertical GAN MOSFET architectures. Interface trap density may be reduced by decreasing the capacitance associated with defects and surface contamination or by selection of a dielectric material with a lower dielectric constant. Fixed charges at the dielectric/semiconductor interface are manifested in hysteresis between forward and reverse voltage sweeps and may be the result of contamination prior to ALD or point defects in the material. Al,0. is an attractive gate dielectric material due to its dielectric constant, which may improve breakdown strength (Fig. 1), but it may suffer from higher memory charge between continuous bias sweeps. SiO, ALD films have lower breakdown and significantly lower leakage currents but show the lowest density of remaining fixed charges between sweeps, suggestive of the lowest DIT of the tested dielectrics (Fig. 2) with the addition of PDA. Results were verified by altering bias conditions during testing in order to accumulate and deplete interface charges. Minor plateaus in capacitance in forward bias indicate the presence of negative fixed interface charges. Additional characterization may be necessary to determine the optimal conditions for DIT reduction for HfO., films, including reduction in PDA temperatures in combination with improved substrate chemical cleans.

Interface Trap Density Characterization of ALD Gate Dielectrics for GaN Power MOSFETs

Digital neural networks (NNs) and the availability of large training datasets have allowed for rapid progress in the performance of machine-based tasks for a wide range of applications including image analysis, sound recognition, and natural language translation. The enhanced capability has, however, come at a computational cost as increased complexity and accuracy have necessitated the need for ever larger deep neural networks (DNNs). One alternative to DNNs is the use of optical processors that have the advantages of ultra-fast processing times and low energy costs. These systems can be employed as stand-alone processors or as front-end accelerators for digital systems. In either case, optical systems are most impactful when used for the linear matrix-vector multiplications that comprise the convolution operations in DNNs as these are often the most computationally burdensome components typically comprising more than 90% of the required floating-point operations (FLOPs) in popular CNNs. In the case of image analysis, free-space approaches are attractive as spatial multiplexing can be readily achieved as well as the fact that an optical front-end can potentially be integrated directly with an imaging system. The most traditional approach to free-space based optical image processing is the use of 4f optical correlators where spatial filters, either passive or dynamic, are placed in the Fourier plane of a 2-lens optical system. Recorded spatial features are then fed to a lightweight digital NN back-end for classification. An alternative approach is the use of diffractive neural networks which utilize cascaded diffractive elements as convolutional layers. Image classification is realized through redistribution of optical energy on the detector plane requiring minimal digital processing. The tradeoff is the need for several diffractive layers as well as coherent illumination, precluding use with ambient lighting. While these approaches have shown benefits in terms of processing speed and energy consumption, they necessitate enlarged imaging systems. Furthermore, none of these approaches utilize the additional information channels, such as polarization, that are available when utilizing an optical front-end. Here, we demonstrate the use of meta-optic based optical accelerators that serve as the convolutional front-end for a hybrid image classification system. Spatial multiplexing is achieved by using a multi-channel metalens for image duplication and a metasurface-based convolutional layer. This system has the advantage of being compact while the use of metasurfaces allows for additional information channels, in this case, polarization, to be accessed enabling both image and polarization-based classification. The hybrid network utilizes end-to-end design such that the optical and digital components are co-optimized while also incorporating statistical noise resulting in a robust classification network. We experimentally demonstrate the classification of the MNIST dataset with an accuracy of 92% as well as 94% accurate classification of polarized MNIST digits. Due to the compact footprint, ease of integration with conventional imaging systems, and ability to access additional information channels, this type of system could find uses in high-dimensional imaging, information security, and machine vision.

Meta-Optic Accelerators for Object Classifiers

Digital manufacturing is revolutionizing the manufacturing industry. Recent breakthroughs in hybrid 3D printing by the EM Lab at the University of Texas at El Paso have made it possible to build three-dimensional parts composed of any distribution of metals, dielectrics, and other materials. This talk will cover some of the new and exciting applications in circuits, electromagnetics, photonics, and metamaterials that are being enabled by digital manufacturing. Electrical circuits can be made three-dimensional where components are placed at any position xyz and oriented at any angle theta-phi. Interconnects can meaner along smooth paths throughout all three dimensions. This creates new degrees of freedom for layout and routing that can make circuits more compact, smaller, and lighter. Shorter trace lengths reduce parasitic impedance to improve power efficiency and increase bandwidth. 3D circuits can be manufactured into unconventional form factors and exploit physics, such as dielectric anisotropy, not easily accessed by planar circuits. Another breakthrough by the EM Lab allows periodic structures to be bent, twisted, conformed, and otherwise spatially varied without deforming the size, shape and spacing of unit cells. Such deformations would weaken or erase the electromagnetic and optical properties of the lattices. The technology was first applied to photonic crystals where discoveries were made that led to the tightest bend of unguided optical beam, refractionless lenses, and photon funneling. The technology was next applied to metamaterials to develop a tool to generate metamaterial lattices for devices designed by transformation optics. The technology is now being used to generate periodic structures across doubly-curved surfaces.

Electromagnetics and Photonics in the Age of Digital Manufacturing

We report our recent results on scalable fabrication of helical slow wave structures (SWSs) applicable in millimeter-through-THz traveling wave tube amplifiers (TWTAs) [1]. The structure is unique in that it has microscale diameter dimensions, a helical geometry, and potentially higher electrical/thermal conductivity than other previously reported self-assembled helices. We fabricate the SWSs by self-assembly of a metal nanomembrane (NM) and electroplating of the helical film, thereby overcoming the inherent trade-off between NM thickness and helix diameter/pitch. Here we focus on our recent efforts on understanding and controlling electrodeposition on freestanding and curved NMs. In particular, we investigate the effect of varying current and temperature on the thickness of the deposited film and its uniformity. In addition, we characterize and justify any changes occurring in the geometry of the helix due to electrodeposition. Fabrication of microscale SWSs started with defining NMs strips by optical lithography, metal evaporation, and lift-off. In our work we used Cr/Au/Cr NMs that have an inherent stress gradient across their thickness. We defined the metal strips onto a bulk Si substrate coated with a sacrificial or release layer such as Ge or GeO, . The released NMs selfassembled into helices with a diameter between 100 and 200 mm upon selective etching of the sacrificial layer by a XeF,, plasma. Helix diameter and pitch are controlled by varying the thickness, the elastic modulus, the residual stress, and the in plane geometry of the NMs. The electroplating procedure employs a two-electrode electrochemical setup with the self-assembled helix and a platinized mesh serving as cathode and anode, respectively. A sulphatebased gold solution is used for the process. We use pulsed current source with variable frequencies to obtain uniform electrodeposition of an Au film with a thickness of 1-2 mm depending on the electrodeposition parameters. In all investigated electroplating conditions, we observed uniformly deposited gold with lower roughness than the skin depth of the metal at THz frequencies, which are crucial attributes to minimize losses and heating in a TWTA based on the helical SWS. Reference [1] Prakash, Divya J., Matthew M. Dwyer, Marcos Martinez Argudo, Mengistie L. Debasu, Hassan Dibaji, Max G. Lagally, Daniel W. van der Weide, and Francesca Cavallo. 2020. “Self-Winding Helices as Slow-Wave Structures for Sub-Millimeter Traveling-Wave Tubes.” ACS Nano, 2021, 15, 1229-1239. doi:10.1021/acsnano.0c08296. Work supported by U.S. AFOSR-Award No. FA9550-19-1-0086

Electroplated Helical Slow-Wave Structures for Millimeter-Through-THz Vacuum Electronic Devices

B-phase MgGaO ternary alloy thin films of different Mg compositions were grown by using oxygen plasma assisted molecule beam epitaxy (MBE). The atomic ratios of Mg and Ga in sample A, B, and C were recorded as 11.15 at.%/88.85 at.%, 23.29 at.%/76.71 at.%, and 36.35 at.%/63.65 at.%, respectively, which were measured by energy-dispersive X-ray (EDX) spectroscopy. The samples were characterized by a scanning electron microscope (SEM), showing that the surface becomes rougher in samples with higher Mg contents. Three typical monoclinic structure diffraction peaks located at 19.12°, 38.50°, and 59.14°, which correspond to the B phases of (-201),(-402), and (-603) were investigated by X-ray diffraction (XRD), and all these diffraction peaks exhibit an obvious blue shift compared with that of reference B-Ga,0.. Raman spectra were investigated by a confocal Raman microscope equipped with a high-resolution laser centered at 532 nm with a power of 60 mW. Four out of ten A_ and four out of five B_ Raman-active optical phonon modes were observed. The reduced peak intensity of A (2)(9) A (10) B (2)- (3), and B 8 indicates that Mg * atoms have replaced the position of Ga * ions in both octahedral and tetrahedral chains. The ultra-wide bandgap absorption and transmittance spectra were measured using a UV-Vis-NIR spectrophotometer. Ultra-wide bandgaps of 4.98, 5.05, 5.20, and 5.30 eV were measured for pure Ga,0x, sample A, B, and C, respectively with all transmittances of light over 80% in the visible spectrum region. Temperature-dependent photoluminescence (PL) spectra were investigated by a 325-nm laser with temperatures ranging from 13 to 300 K, revealing only intermediate level transitions, which decrease with the increase of temperature. A MSM solar-blind ultraviolet photodetector (PD) was fabricated based on MgGaO films with Pt/Au electrodes. Photoresponse has been studied by typical dark and irradiated wavelength dependent I-V curves.

Characterization of β-Phase MgGaO Thin Films Grown by Molecular Beam Epitaxy

Gallium oxide (Ga2o3.) is an ultra-wide bandgap semiconductor (4.85-5.3 eV) with emerging applications in power electronics because of its high thermal stability, large breakdown voltage and high dielectric constant. Ga, 03 occurs in the a, B, y and k(€) polymorphs having trigonal, monoclinic, cubic normal spinel and orthorhombic structures, respectively. B- “Ga, 03 is thermodynamically stable and produced in melt-grown substrates. Recently, k- -Ga,0. has accrued increased interest because it has demonstrated stability at temperatures 2 700 °c! and its large spontaneous polarization could be exploited in heterostructures” for high electron mobility transistors. In this study, metal organic chemical vapor deposition (MOCVD) was used to grow epitaxial Ga,0. films under different growth conditions including temperature, growth rate, and diluent gas flow rate. The growth experiments were conducted in a vertical, low-pressure, cold-wall MOCVD reactor using triethylgallium (TEGa) and 0, precursors and commercially available 0.15 off-axis (toward m-plane) c-plane sapphire. No was used as both the carrier gas for TEGa and the diluent gas. The chamber pressure was held at 20 Torr. The growth rate was controlled by the TEGa flow rate which ranged from 0.29 sccm to 2.1 sccm. The diluent gas flow rate was varied from 4 slm to 8 sim. The O flow rate was maintained at 500 sccm. The temperature was constant for each growth but varied from 470°C to 570 C. Phase composition and microstructural evolution of the films were investigated using different analytical tools including the X-ray diffraction (XRD), scanning electron microscopy (SEM), high-resolution transmission electron microscopy (HRTEM) and scanning transmission electron microscopy (STEM). XRD and SEM revealed that the top layer varied in phase composition between ~100% k-Ga,0, and ~100% B-Ga,0.; the surface microstructure ranged from poorly coalesced to completely coalesced grains as a function of growth temperature, growth rate, or diluent gas flow rate. In general, it was found that the k-phase tends to grow at lower temperatures and higher growth rates (higher TEGa flow rates). The growth of nominally single- phase k-Ga 90 within the top layer was observed in a temperature range between 500° C and 530° C. Below 470° C, only amorphous Ga 90,was obtained; above 570° Cc only the B-phase was deposited. HRTEM and STEM of a film grown at 530° C revealed the initial pseudomorphic growth of 3-4 monolayers of a-Ga,0., a 20-60 nm transition layer that contained both B- and y-Ga,0., and a top ~700 nm thick layer of phase-pure k-Ga,0,. H.Y. Playford, A.C. Hannon, E.R. Barney, and R.|. Walton, Chem. Eur. J. 19, 2803 (2013). R. Roy, V.G. Hill, and E.F. Osborn, J. Am. Chem. Soc. 74, 719 (1952). Y. Oshima, E.G. Villora, Y. Matsushita, S. Yamamoto, and K. Shimamura, J. Appl. Phys. 118, 085301 (2015). J. Lee, H. Kim, L. Gautam, K. He, X. Hu, V. Dravid, and M. Razeghi, Photonics 8, 17 (2021). P. Ranga, S.B. Cho, R. Mishra, and S. Krishnamoorthy, Appl. Phys. Express 13, 061009 (2020). On K. Jiang, J. Tang, M. J. Cabral, A. Park, L. Gu, R. F. Davis and L. M. Porter, J. Appl. Phys. (2022)

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Process-Induced Variability of SiC DMOSFET Short Circuit Capability

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Interface Trap Density Characterization of ALD Gate Dielectrics for GaN Power MOSFETs