United States

We live in a world of data-intensive systems and applications, fueled by the integration of AI tools in our daily routines, driving exponential growth in our memory and storage systems capacity. Our memory and storage hierarchy has developed around existing technology, and while there is still significant room for optimization in this space, we see a greater need to introduce new technologies in the future. To meet the evolving demand for higher performance, lower power, improved reliability and cost, the memory hierarchy is seeing an expansion with new memory solutions. At the same time, we are seeing a convergence of storage and memory applications. Significant opportunities are emerging, for high bandwidth and high-capacity memories to improve the bottleneck and performance limitations of traditional DDR memory systems. On the other end of the hierarchy, storage solutions are evolving into high performance storage space while continuing to drive cost scaling. Such new memory and storage solutions require innovation in materials, device, process, packaging, and systems technology. While we continue to grapple with cost, performance, and reliability optimization challenges, we must also find solutions that enable sustainable manufacturing and products. In this keynote, we will present some of the challenges the industry is facing and opportunities ahead to continue to meet the requirements across the applications landscape.




IRPS 2022 Main Conference 

Transformation of Memory and Storage Hierarchy: Enabling high performance, reliable, and sustainable compute applications

micron

keynote

memory

## Welcome!
"I am excited to welcome you to this year’s edition of the Conference on Empirical Methods in Natural Language Processing! Importantly, it marks the 30th edition of EMNLP. With over 8,000 submissions, more than 3,000 accepted papers, and thousands of attendees, we have come a long way from that first
workshop, which had 14 accepted papers. As the field looks ahead, Suzhou is the fitting location for celebrating this milestone: rooted in a long literary tradition, yet modern and forward-looking, and home to a large share of the NLP community." 

*Message from the General Chair, Dirk Hovy*

EMNLP 2025

Celebrate 30 Years of EMNLP! 
EMNLP 2025 will be held in Suzhou, China from November 5th to November 9th, 2025.

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

For the first time, a reliability study on degradation of InGaAs/GaAs nano-ridge p-i-n diodes monolithically integrated on Si by nano-ridge engineering (NRE) is reported. Wafer-level constant current stress in forward bias shows a gradual power law aging of both forward and dark current. Current crowding and Joule heating near the p-contact are responsible for the degradation in forward bias region. Indications of defect formation and Ti diffusion at the metal/GaAs interface are witnessed. The electrical stress-induced leakage current builds up at reverse bias region, pointing to the degradation of crystal quality. A sintering process lowers the p-contact resistance and improves electrical stability. The high aspect-ratio of the trenches leads to effective threading dislocation trapping: no dislocations have been observed to penetrate the active region during the 5000s stress time. This early work sheds light on realizing electrically robust GaAs diodes on Si and reliable monolithic lasers.

Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon

Channel percolation in Ferroelectric FET (FeFET) due to random spatial distribution of switched domains reduces the number of accessible threshold voltage (VTH) states, thus posing a profound reliability challenge for neuromorphic. However, channel percolation is not universally present in FeFET and only exists when the channel regions underneath the domains have negligible interaction. In this work, we perform a comprehensive evaluation on the parameters that impact neighbor interaction, and hence channel percolation. We reveal i) weak gate control with thick ferroelectric layer enhances neighbor interaction and suppresses percolation; ii) higher temperature can also reduce percolation by weakening the gate control. 

Supressing Channel Percolation in Ferroelectric FET for Reliable Neuromorphic Applications

In this work, we demonstrate that proper engineering of VTH in ferroelectric FET is necessary to ensure correct array operation for in-memory computing applications. We highlight that for all current-based computing operations, it is necessary to keep both the low-VTH and high-VTH states positive to cut off the leakage for grounded unselected cells. To reach that design target, we systematically evaluate various design options for VTH engineering, including the gate metal work function, the body bias, and the buried oxide thickness, using calibrated TCAD. We establish the design guidelines for VTH engineering to ensure the successful operation of in-memory computing.

Ferroelectric FET Threshold Voltage Optimization for Reliable In-Memory Computing

We present an analysis of the impact of passivation and gate foot etching on the reliability and trapping behavior of RF GaN HEMTs. The study is based on HTRB experiments and DCT analysis.  We demonstrate that: passivation significantly impacts on the stability of the gate-leakage characteristics during HTRB stress; best stability is obtained through the use of LPCVD. DCT measurements reveal the presence of two trapping processes;  the slower time constant depends on the processing parameters and increases in presence of optimized gate-foot etch and passivation. The results presented provide information for the optimization of GaN RF devices.

GaN RF HEMT Reliability: Impact of Device Processing on I-V Curve Stability and Current Collapse

For plasma process induced damage (PID) qualifications stresses are necessary to detect lifetime reduction risks. JEDEC JEP001 requires HCS, BTS, and TDDB stresses, or a revealing stress for this detection. Due to the large number of devices that should be tested the revealing stress can be preferable. This paper reviews the two main options for the revealing stress for thick oxides, constant gate current (CGC) versus constant gate voltage (CGV) stresses. The results are also intended as input to the discussions in the current JEDEC 14.2 PID standard working group.

Revealing stresses for plasma induced damage detection in thick oxides

IoT edge devices are expected to have high-capacity and low-power storage memory, as well as smart data processing capability such as machine learning and AI, to fully utilize big-data by co-working with cloud computing system. Such edge intelligence requires energy-efficient data movement and computation, which opens new challenges and opportunities to integrated devices, circuits and systems. In this paper, we introduce monolithic 3D integration technologies of (1) high-density embedded memory and (2) in-memory computing, both of which are enabled by oxide semiconductor FETs and memory devices, for AI acceleration. We address key reliability issues regarding manufacturability for each technology. 

Reliability characteristics of mobility-enhanced FET and wakeup-free ferroelectric capacitor enabled by InGaZnO for machine-learning accelerator in AI chip

Reliability research is shifting from from devices to circuits. Wide range of operating conditions and different scaling factors for reliability modes presents a unique challenge to predict circuit lifetime. We present the “Q&amp;R on Chip” (QROC), a unified, oven-less and scalable platform for circuit reliability evaluation. State-of-the-art QROC chips helps evaluate various modes such as aging, gate-oxide breakdown and thermal reliability.  A new test platform with an on-board FPGA, PC interface and heater socket for temperature control is designed. Preliminary aging stress data from more than 15000 instances of ring-oscillators comprised and 107 different RO is presented.

On-Chip (QROC): A Unified, Oven-Less and Scalable Circuit Reliability Platform

The source-drain punch-through current in off-state TDDB stress (OSS) is shown to significantly affect off-state breakdown behavior. This paper introduces a modified methodology for conducting OSS in scaled tri-gate devices at accelerated conditions that avoids artifacts associated with punch-through while enabling reliability risk assessment. The methodology is validated for both NMOS &amp; PMOS devices and provides consistent degradation mechanism. Finally, it is shown that on-state gate-oxide TDDB remains the reliability limiter compared to OSS TDDB. 

Method to evaluate off-state breakdown in scaled Tri-gate technologies

In past decades, continuous technology advancement has been accelerating semiconductor evolution to enrich our daily life. Today, advanced logic technologies are the key drivers for Mobile and HPC segments. Incorporating additional specialty technologies (HV, RF, Non-Volatile Memory, MEMS, CIS, etc.) empowers new applications. It also enable further customization of process and designs that is essential to fulfill different product needs. However, the past standardized methodologies with logic based bias and failure criterion fall short of enlarging technology envelope on top of meeting field expectation. Therefore, TSMC has been developing a circuit-based qualification approach offering accurate assessment on reliability lifetime to direct device offering and customizing process for specific product usage. A comprehensive reliability platform covering from design stage to mass production has been deployed for different applications which will be a general practice for future technologies. Along the way, we have been establishing our partnership across IP providers, circuit and system designers as well as reliability communities to have joint development by DFR (design for reliability) and DFT (design for testing). This new ecosystem on reliability incorporated DTCO (Design-Technology Co-optimization) is the next key focus to unleash more innovations and maximize process technology value with fast time-to-market.

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Wafer-Level Aging of InGaAs/GaAs Nano-Ridge p-i-n Diodes Monolithically Integrated on Silicon

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