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Using Apache TVM for automated end-to-end HW/SW co-design for deep learning.

NAML 2022

Using Apache TVM for End-to-end HW/SW Co-design

deelp learning; hw/sw co-design

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technical paper

Naval Information Warfare Center Pacific is partnering with AFCEA San Diego chapter to host the workshop.

The NAML workshop is an opportunity for researchers from Navy research and development centers and our partner organizations to exchange technical ideas and to come together as a team.

The goals of NAML are:

To spread awareness of current machine learning research relevant to Naval applications

To connect machine learning researchers with experts in military requirements

To build and strengthen collaborations within the defense research community


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Registration for this workshop has now closed.

Naval Information Warfare Center Pacific is partnering with AFCEA San Diego chapter to host the workshop. The NAML workshop is an opportunity for researchers from Navy research and development centers and our partner organizations to exchange technical ideas and to come together as a team.

The goals of NAML are:

To spread awareness of current machine learning research relevant to Naval applications

To connect machine learning researchers with experts in military requirements

To build and strengthen collaborations within the defense research community



Autonomous Systems consist of different systems working together so they can sense, plan, and act to a dynamic environment. There is much confusion on what autonomous systems are. This session will explain what autonomous systems are and how machine teaching and simulation can collaborate to create autonomous systems. Machine Teaching is critical to autonomous systems. It is based on reinforcement learning. The differences between machine teaching and machine learning will also be clarified.

Understanding Autonomous Systems

Reinforcement learning (RL) is an effective method for solving problems that require autonomous agents to learn the best way to act in complex environments. RLlib is a powerful tool for applying reinforcement learning to problems where there are multiple agents or when agents must take on multiple roles. There exist many resources for learning about RLlib from a theoretical or academic perspective, but there is a lack of materials for learning how to use RLlib to solve your own practical problems. This tutorial helps to fill that gap. We show you how to apply reinforcement learning to your problem by taking you through a custom environment and demonstrating how to apply RLlib to that environment. We make the code available on GitHub.

Tutorial: RLlib for Deep Hierarchical Multiagent Reinforcement Learning

Although Convolutional Neural Networks (CNNs) achieve high accuracy on image recognition tasks, they lack robustness against realistic corruptions and fail catastrophically when deliberately attacked. Previous work suggests that CNNs with representations similar to primary visual cortex (V1) are more robust to adversarial attacks on images than current adversarial defense techniques. However, these approaches require training on large-scale neural recordings or handcrafting classical neuroscientific models. Motivated by long-standing evidence that neural activity in V1 and other sensory areas is sparse, we develop a class of hybrid CNNs, called LCANets, which feature a frontend with recurrent lateral competition. We demonstrate competitive accuracy of LCANets on action recognition datasets and show that LCANets are significantly more robust to image corruptions and adversarial examples than both standard CNNs and adversarially-trained CNNs. Our results demonstrate that recurrent lateral competition plays a large role in forming sparse and robust V1-like representations when incorporated into CNNs.

CNNs With a Neuromorphic Sparse Coding Frontend are More Robust to Adversarial Attacks

Today, essentially all computing is done with Boolean logic and binary numbers, requiring all manner of error correction codes to keep the most significant bits straight. But in the realm of machine learning, what if instead every bit was equally (in)significant? Consider two randomly generated strings thousands of zeros and ones long, about 50/50 split. Normally, about half the bits will be different between the two strings. If the number of differences is less than half though, the strings as a whole must be related. Even a large number of errant bits will not change the strings’ similarity. This creation and measurement of similarity between very large strings of bits (or numbers) is called hyperdimensional computing (HDC). 

Though not quantum mechanical, a kind of superposition of information across each of the thousands of bits enables machine learning capabilities even Deep Neural Networks (DNN) struggle with, such as learning from a single example or combining the learning from several different sensor modalities. One can even dynamically reprogram swarms of robots in a contested environment – the new program intelligible from a single binary string even with 30-50% noise.

What if we started training artificial neural networks (ANN) to learn and recall these strings: not memorizating or autoencoding but rather “resonating” like a tuning fork? This “resonance” training paradigm suddenly enables even more capabilities not possible with traditional DNNs today such as learning new categories “on the fly” without retraining the whole network from scratch. Such attractor state networks (ASN) lend themselves to modular design, allowing new categories to be added or shared amongst other ASNs. This combining of HDC with “resonance” ANNs is a potential game changer for machine learning, establishing mathematically rigorous engineering design rules instead of the unintelligible black boxes of DNNs today.

Hyperdimensional computing can be implemented in traditional computing hardware, but large size, weight, and power savings are possible by including memristors crossbars into the ML ensemble. The Pipeline for Novel Neuromorphic Hardware (NeuroPipe) Applied Research for Advancement of Priorities (ARAP) is working to bring not only novel neuromorphic computing hardware like memristors to the field but also develop the next generation of machine learning algorithms such as these.


NeuroPipe ARAP Hardware & Algorithms


Robots are increasingly deployed to solve complex real-world tasks that require  continuous processing of their observations only to be constrained by their on-board resources.  Energy-efficient control of mobile robots is one of the limiting factor in having robots deployed  to perform in-space assembly of structures. Spiking Neural Networks (SNNs) deployed on  neuromorphic processors provide an energy-efficient solution that could also facilitate building  intelligence similar to living creatures for robots. 
Neuromorphic architectures imitate the behavior and function of biological nervous  systems by implementing networks of artificial neurons and synapses that benefit from low  power consumption. These computing platforms emulate their biological counterparts by  distributing both computation and memory among a large number of computation units, each  passing information, via asynchronous spikes, to hundreds or thousands of other computational  units, like neurons would do through synapses. 
Over time, different digital neuromorphic architectures like Intel’s neuromorphic  technology, code named Loihi [1], have replicated many characteristics of SNNs in hardware.  Despite the advantages of neuromorphic hardware (e.g., high speed and energy efficiency)  there are few algorithms that utilize it for in situ robot control. Recent work by Michaelis et al. [2], proved the theoretical feasibility of using Intel’s neuromorphic technology for trajectory  generation on hardware, but fails to employ the strategy with robotic hardware (simulated or in  situ). Michaelis’ work presents a biologically plausible approach that also promised a control  relevant timescale.  
His work is based on Reservoir Computing, specifically, Liquid State Machines,  implemented as biologically plausible anisotropic networks. In Michaelis’ work for trajectory  generation, the liquid layer is implemented as an anisotropic network, based on a biologically  
inspired rule for forming spatially asymmetric non-plastic connections, similar to the ones that  have been observed to activate in human and mammal brains [3]. It is believed that correlated  spatial anisotropic connectivity is what makes learning faster and more efficient. Michaelis et 
Distribution A — Approved for public release, distribution is unlimited 
al. [2], make use of this anisotropic network idea from Spreizer et al. [3] and show the feasibility  of using an architecture that integrates it for trajectory generation.  
In this work we close the gap between theoretical formulation and practical applications  by implementing the missing components to enable Kinova Gen3, a 7 degree of freedom  robotic arm, to use this type of neural network on Intel Kapho Bay Loihi for trajectory  generation.  
Demonstrating neuromorphic capabilities for robotic control is of high interest at NRL  due to the appeal of high performance and energy efficiency that neuromorphic hardware  presents. The success of this strategy has a big impact on different projects at NRL that are investigating: neuromorphically controlled multi-limbed robotic systems for Naval ship  maintenance tasks, neuromorphically controlled multi-limbed space truss walking robot that  can autonomously assemble truss elements to construct large space structures in orbit, and the  capabilities of memristor-based neuromorphic processors. 

References: 

[1] Davies, M., Srinivasa, N., Lin, T.-H., Chinya, G., Cao, Y., Choday, S. H., et al. “Loihi: a  neuromorphic manycore processor with on-chip learning.” IEEE Micro (2018). 
[2] Michaelis, Carlo, Andrew B. Lehr, and Christian Tetzlaff. “Robust trajectory generation for  robotic control on the neuromorphic research chip Loihi.” Frontiers in neurorobotics 14 (2020). 
[3] Spreizer, Sebastian, Ad Aertsen, and Arvind Kumar. “From space to time: Spatial  inhomogeneities lead to the emergence of spatiotemporal sequences in spiking neuronal  networks.” PLoS computational biology 15.10 (2019).
Distribution A — Approved for public release, distribution is unlimited 
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Neuromorphic Hardware Anisotropic Reservoir Trajectory Generation and execution with Robotic Arm

In this work we present a spiking neural network for the adaptive control of a simulated Kinova Gen3 7-DOF arm. This work extends the Recurrent Error-driven Adaptive Control Hierarchy (REACH), developed as a computational model of the primate motor control system, which had previously been implemented for the operational space control of a 3-DOF arm restricted to the horizontal plane. The REACH model is divided into kinematics control, responsible for transforming the control signal from end-effector (hand) space to joint-space, and dynamics control, responsible for accounting for the effects of gravity and inertia on the system. Additionally, a nonlinear adaptive control component learns online to correct for errors that arise during movement as a result of internal model inaccuracies or external perturbations. Due to the increased complexity of the 7-DOF system, the process for training the REACH model required a different approach than the 3-DOF implementation. Here, we utilize a hybrid approach to training that takes advantage of both deep learning and the circuit building methods from the Neural Engineering Framework (NEF). The NEF allows us to both quickly build highly optimized components performing computations on low-dimensional input, as well as integrate these networks directly with those trained using deep learning, which provides a more exhaustive sampling of high-dimensional state space. We analyze the performance of the spiking control network on a benchmark task compared to both an analytic controller and a rate-mode version of the control network. Lastly, we discuss the process of training the network to run on the highly-efficient neuromorphic chip from Intel, the Loihi, and provide initial results from simulation in a Loihi emulator.

Adaptive spiking control of a 7 DOF arm

Synaptic plasticity poses itself as a powerful method of self-regulated unsupervised learning in neural networks. A recent resurgence of interest has developed in utilizing Artificial Neural Networks (ANNs) together with synaptic plasticity for intra-lifetime learning. Plasticity has been shown to improve the learning capabilities of these networks in generalizing to novel environmental circumstances. However, the long-term stability of these trained networks has yet to be examined. This work demonstrates that utilizing plasticity together with ANNs leads to instability beyond the pre-specified lifespan used during training. This instability can lead to the dramatic decline of reward seeking behavior, or quickly lead to reaching environment terminal states. This behavior is shown to hold consistent for several plasticity rules on two different environments across many training time-horizons: a cart-pole balancing problem and a quadrupedal locomotion problem. We present a solution to this instability through the use of spiking neurons.

Stable Lifelong Learning: Spiking neurons as a solution to instability in plastic neural networks

DARPA’s Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler’s capabilities across two critical, high-bandwidth application areas: 5G networks and image processing.

Real Time Machine Learning: Automated Flows Enabling Concept to Chip

VeriGOOD-ML is an automated methodology for generating machine learning (ML) hardware for DNN and non-DNN ML algorithms. The VeriGOOD-ML generator takes as input a high-level description of an ML algorithm in a standard format such as ONNX, and outputs Verilog RTL code, with no human in the loop. The Verilog RTL is then translated through a back-end design flow to GDSII, driven by a design planning approach that is well tailored to the macro-intensive nature of ML platforms. VeriGOOD-ML uses three approaches to build ML hardware: (1) the TABLA platform uses a dataflow architecture that is well suited to non-DNN ML algorithms; (2) the GeneSys platform, with a systolic array and a SIMD array, is optimized for implementing DNNs; and (3) the Axiline approach synthesizes small ML algorithms by hardcoding the structure of the algorithm into hardware, thus trading off flexibility for performance and power.

The Verilog generator is complemented by an approach that performs design space exploration of the configurations of each hardware engine to determine the best implementation of the hardware. The performance metrics of the implemented hardware are significantly affected by the configuration of the hardware platform and the physical implementation from RTL to GDS. Key metrics include the power, performance, and area (PPA) of the hardware engine, and the power, execution time, and accuracy of the ML algorithm at the system level. The talk overviews the overall methodology, from architecture to back-end design to hardware implementation, and presents the results of VeriGOOD-ML on a set of ML benchmarks.

Physically-aware Automated ML Hardware Generation using VeriGOOD-ML

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements.
However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages.
Agile hardware design tools based on compiler techniques, instead, can quickly produce an application specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description.
We present the SODA Synthesizer, a modular and opensource hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multi-level representations to progressively lower and optimize the input code.
Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 GFLOPS/W (32-bit precision) efficiency on typical convolutional neural network operators.

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