United States

For the design of reliable ICs the application of accurate transistor aging models is indispensable. However, especially for modern deeply-scaled technologies modeling NBTI induced aging poses significant challenges as transistors can not be characterized individually but need to be described as a statistical ensemble. We make use of a dedicated array structure enabling the collection of a large data-set at reasonable experimental time. Note that by using an extensive data-set the statistical confidence can be maximized. We present a modeling approach based on physical considerations to describe the aging of SRAM-sized transistors under consideration of statistical effects. Our approach applies a modified defect-centric model under consideration of RTN to describe the time-dependent Vth distribution. Furthermore, we introduce a simple method to extract parameters describing the distribution. Additionally, we show that our approach provides great flexibility regarding stress conditions as well as scalability to different transistor dimensions, which makes it ideal for applications such as circuit simulation.

IRPS 2022 Main Conference 

Efficient Evaluation of the Time-Dependent Threshold Voltage Distribution Due to NBTI Stress Using Transistor Arrays

transistor array

nbti variability

compact modelling

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

New multi-layer ALD HfO2/Al2O3/HfO2
laminate film with a capacitance density 8.3 fF/um2 is evaluated in a MIM capacitor, in 65nm node process, for emerging applications in the automotive space which require higher use voltage and temperature than CMOS logic and DRAM applications. Apart from the typical considerations such as leakage current, capacitance linearity etc. the dielectric relaxation current behavior is also studied. We have performed a thorough reliability study on these films and demonstrate that they meet the stringent requirements for automotive safety applications.

High-k MIM dielectric reliability study in 65nm node

This paper will discuss how deep data analytics based on Universal Chip Telemetry™ (UCT) offers a new approach to lifecycle health and performance monitoring in advanced electronics. By combining on-chip monitoring with machine learning inference in the cloud and edge, production quality is improved through advanced latent defect detection, while lifetime reliability is increased through degradation monitoring and predictive fault detection.

Applying Universal Chip Telemetry to Detect Latent Defects and Aging in Advanced Electronics

Simulations based on first-principle modeling of material structural features determining electrical properties of a CNT memory cell allow to identify a range of operation conditions delivering desirable device characteristics. This approach designates the path for optimization of the CNT memory device structure to meet the performance requirements.   

Combining measurements and modeling/simulations analysis to assess carbon nanotube memory cell characteristics

Contacts stability versus thermal budget is a major concern in 3D sequential integration. We experimentally investigate the thermal stability of n-type contacts on Si and p-type contacts on SiGe in terms of specific contact resistivity (ρc). An improved ρcn performance featuring lower magnitude and better thermal stability has been demonstrated for Ti silicide contacts on n+-Si with Ge pre-amorphization implantation (PAI). For p-type contacts, it is found that Ni has lost its high work function advantage on p++-SiGe and Ti germanosilicide contacts show ρcp outperformance. CMOS contact scheme based on single Ti instead of dual Ti and Ni has hence been evidenced to be more suitable for 3D sequential integration.

Investigation on Contacts Thermal Stability for 3D Sequential Integration

This paper studies the use of 1-selector-1-resistor (1S1R) devices as the cross-point components in a crossbar array for deep neural network (DNN) training. Two training algorithms—minibatch gradient descent (MBGD) and a low-rank approximation to MBGD—are evaluated with compact models of ovonic threshold switching (OTS) selectors considering several reliability issues, and resistive random-access memory (ReRAM), a type of emerging non-volatile memory (NVM) device. We explore various reliability concerns of the OTS selectors including the low on-state conductance, threshold voltage variation, and internal voltage offset, etc. and propose corresponding techniques to overcome the reliability challenges.

Effect of OTS Selector Reliabilities on NVM Crossbar-based Neuromorphic Training

In this paper, the long term data retention characteristics consisting of three main charge loss mechanisms, detrap, trap-assisted tunneling (TAT), and lateral migration (LM), are investigated in charge trap (CT) 3D NAND flash memory. Three mechanisms were completely separated through experiment design, and each activation energy (Ea) was extracted with Arrhenius model well. The detrap mechanism shows the largest Ea, followed by LM and TAT mechanisms. It is interesting that the contribution rate (CR) of each mechanism is related to time-constant (t) in the early part of bake time, and depends on the final charge loss in the latter part of bake time. It is inferred that the retention bottleneck is low program level state at high temperature and is high program level state at low temperature. TAT mechanism dominates the final charge loss regardless of temperature region and program level state. In addition, an effective method is proposed to suppress the LM effect.



Investigation of Retention Characteristics in a Triple-level Charge Trap 3D NAND Flash Memory

Scaled (LG = 0.1 μm) GaN HEMT technology is currently pursued for high-frequency applications (such as 5G), requiring high current/speed and blocking capability. However, traps introduced with intentional Fe doping yield time-dependent breakdown voltage (VBR), seriously affecting reliability. Here, we investigate the role of Fe traps by pulsed I-V characterization performed at different pulse durations (TOFF). A TOFF-dependent VBR is observed on tested devices and is ascribed to the time-dependent occupancy of deep acceptors in the buffer layer. More specifically, the decrease in VBR for short pulses is attributed to the increased leakage due to the reduced ionization of Fe-traps. This interpretation is supported by 2D numerical simulations.

Fe-Traps Influence on Time dependent Breakdown Voltage in 0.1 µm GaN HEMTs for 5G applications

On-chip degradation monitoring enables reliable recycling of chips in the context of circular economy by assessing their degradation and thereby inferring their remaining lifetime. Implementations of such monitors have already been presented typically relying on ring-oscillator-based circuits to evaluate degradation undergone by ICs. However, these approaches are not able to distinguish between the physical degradation and the time since fabrication and they can be tampered with high temperature annealing. In this work we present a new concept of degradation monitor circuit, which can obtain the age of the chip and detect if the chip has undergone tampering through high-temperature annealing.

A Ring-Oscillator-based Degradation Monitor Concept with Tamper Detection Capability

Owing to its high power, high efficiency, high gain and high frequency capabilities RF-GaN technology has not only dominated satellite, aerospace and telecom industry but also been tapped as the most promising candidate for 5G technology extension to millimeter wave (MMW) applications. Excellent device performances with output power density (Pout) exceeding 3 W/mm and peak power added efficiency (PAE) above 35 % have been demonstrated by Wolfspeed's 5G-MMW capable 28 V, 150-nm gate length (V5) GaN on SiC technology. In this work we show the comprehensive DC (both on and off state) and RF reliability assessment and lifetime projection (both DC and RF) of such MMW capable 28 V rated 150-nm gate length process technology (G28V5). The on-state and off-state results coupled with the reliability without hermiticity (RWOH) capability and intrinsic reliability assessment up to 31.5 GHz demonstrate the maturity and reliability of V5 technology as a true candidate for MMW applications.

DC & RF Reliability Assessment of 5G/mmW capable GaN HEMT Process

Fault injections and attacks on an integrated circuit (IC) chip using a variety of physical measures are reviewed. Laser fault injection (LFI) is highlighted for the essential vulnerability on the backside of an IC chip in flip-chip packaging. On-chip voltage waveform monitoring characterizes the voltage peaks induced by LFI and establishes the detection scheme against LFI attacks. The backside buried metal (BBM) technique is deployed by preventive measures for shielding from laser exposure, for avoidance and also waring of invasive laser attacks. The alleviation of backside LFI is proven by Si experiments with on-chip waveform monitoring.

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High-k MIM dielectric reliability study in 65nm node

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