United States

Reliability qualification of HV interconnects is more complicated due to additional consideration of inter-metal impacts under the influence of HV operation. Unlike intra-metal structure, the film stack and bottom physical profile of inter-metal structure is uneven. This explains the reliability response showing dependence on metal line width and bias polarity. We show the E-field distribution is not uniform with the highest E-field density at the bottom corners of metal line. Hence, for a complete inter-metal TDDB reliability qualification, the impacts from test structure design, process variation, and testing methodology need to be considered.

IRPS 2022 Main Conference 

Insights on Inter-metal Reliability Assessment of High Voltage Interconnects

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

poster

The current understanding of key reliability phenomena such as leakage and Random Telegraph Noise (RTN) is still incomplete. Models exist that explain simple cases (2-level RTN), yet experimental reports showed the occurrence of complex cases (e.g., coupled RTN, anomalous and temporary RTN) that deserve deeper investigation. In this paper, we focus on the often overlooked role of trapped charge in the electrostatic coupling among defects, entailing a multi-body problem, and on the related effects on leakage and RTN. The electric field in the dielectric is found to be usually dominated by the trapped charge rather than by the applied voltage, defying common beliefs and elegantly explaining some of the aforesaid complex scenarios. We demonstrate that such defects interactions are responsible for a strong modulation of the capture and emission time constants over time. Moreover, we highlight how defects capture/emission source/destination can change with the local field and therefore with the applied voltage, which gives rise to non-monotonic trends in tc/te vs. applied voltage plot. This last point reveals that the classical formula adopted for the estimation of the defects vertical position within the dielectric is oversimplified and may lead to significant errors. The results of this study advance the understanding of leakage and RTN, and can be useful for the design of applications such as low-power Physical Unclonable Functions and True Random Number Generators. 

The Relevance of Trapped Charge for Leakage and Random Telegraph Noise Phenomena

This paper reports BTI trends in high-voltage transistors for memory periphery devices with SiO2/Poly and High-K/Metal gate stacks. For PBTI, we present an extension to the typical power law kinetics that is related to the creation of interface states due to hot electrons transported through the gate oxide. This extension enables a good fit of accelerated test data and, thereby, lifetime extrapolation. We then explore EOT and gate stack trends in PBTI. For NBTI, we report gate stack, EOT, and thermal budget trends.

BTI of High-Voltage Logic-for-Memory Devices

We report a record SC robustness of a novel vertical GaN Fin-JFET. This Fin-JFET has an 800 V avalanche breakdown voltage (BVAVA). The tSC is measured to be 30.5 us  at 400 V and 11.6 us  at BVAVA.  As far as we know, this is the first report of a power transistor with robust short-circuit ruggedness at BVAVA. The underlying mechanism is the unique avalanche-through-fin which is verified by TCAD simulation and UIS test. These results alleviate the concern of SC robustness of GaN devices and demonstrate the potential of vertical GaN Fin JFETs in future power applications.

Vertical GaN Fin JFET: A Power Device with Short Circuit Robustness at Avalanche Breakdown Voltage

This work investigates both avalanche behavior and failure mechanism of 3 kV GaN-on-GaN vertical P-N diodes, that were fabricated and later tested under unclamped inductive switching (UIS) stress. The goal of this study is to use the particular avalanche characteristics and the failure mechanism to identify issues with the field termination and then provide feedback to improve the device design. DC breakdown is measured at the different temperatures to confirm the avalanche breakdown. Diode’s avalanche robustness is measured on-wafer using a UIS test set-up which was integrated with a wafer chuck and CCD camera. Post failure analysis of the diode is done using SEM and optical microscopy to gain insight into the device failure physics.


Study of Avalanche Behavior in 3 kV GaN Vertical P-N Diode Under UIS Stress for Edge-termination Optimization

In this paper, a simple circuit is incorporated in a 650V E-mode GaN HEMT process technology to protect all terminals against ESD stress from any direction. Even in the worst case, the gate subjected to negative ESD pulse with respect to grounded drain, the 650V E-mode HEMT can still pass 5kV HBM.

Incorporation of a Simple ESD Circuit in a 650V E-Mode GaN HEMT for All-Terminal ESD Protection

Antenna rules relating to well charging is becoming an important aspect to consider in the design rule checks apart from the conventional antenna to gate ratio design rules. In this paper, we provided a better understanding of the well charging phenomena with different layout configurations and introduced a new power law correlation with well exponent based on characterized data. A comparison of well charging design solutions is presented and validated on circuit-like test structures. 

A Deeper Understanding of Well Charging Reliability with Circuit Relevant Test Structures

Reliability testing of modern tantalum capacitors shows the presence of both types, infant mortality (IM) and wear-out (WO) failures. To assure reliable operation, the probability of IM failures should be reduced to below the specified level, and the time of WO inception should be greater than the required useful life of the parts at operation conditions. In this work, several types of MnO2 and polymer cathode tantalum capacitors have been tested at highly accelerated conditions to assess voltage acceleration factors, determine adequate burn-in conditions, and assess the useful life. A modified time dependent dielectric breakdown (TDDB) model has been suggested to explain both types of failure, and a physical mechanism of degradation that is based on migration and reactions of oxygen vacancies explains increase of the defect related, IM failures with the level of stress.

Infant Mortality and Wear-Out Failures in Polymer and MnO2 Tantalum Capacitors

A systematic study of the time-dependent dielectric breakdown of 3D ferroelectric (FE) and antiferroelectric (AFE) Si:HfO2 capacitors is reported. The voltage and temperature acceleration of characteristic breakdown time is studied. The 10 year lifetime extrapolation is projected to be 2.3 MV/cm and 2.7  MV/cm for 20 nm FE and AFE devices respectively. Further, 10 nm AFE devices had projected lifetime at 2.5 MV/cm at 100 °C. The effect of the polarization measurements on the TDDB is studied and the impact to the lifetime extrapolation was found to be minimal.

Reliability of Ferroelectric and Antiferroelectric Si:HfO2 materials in 3D capacitors by TDDB studies

In the advanced technology process, owing to the low and tunable trigger voltage, diode-triggered SCRs (DTSCRs) are widely used in low-voltage applications with extremely narrow electrostatic discharge (ESD) design margins. The breakdown of DTSCRs ESD structure with abnormal leakage current under transmission line pulsing stressing was studied in this work. The physical origins of DTSCRs have been established through failure analysis (FA). The mismatch of the thermal expansion coefficient of local materials results in redundant stress. Such redundant stress induce the structure dislocations and cracks were captured by transmission electron microscopy at atomic scale. A multi-physical simulation is conducted to scrutinize the breakdown transient process.

Nanoscale Analysis of Breakdown Induced Crack Propagation in DTSCR Devices

Short-circuit capability with GaN HEMTs is demonstrated thanks to an integrated Short-Circuit Current Limiter (SCCL) and a commercial gate-driver with DESAT protection. The SCCL is applied to GaN HEMTs to achieve a sufficiently long short-circuit withstanding time (SCWT) while retaining competitive on-state resistance. The SCWT is tuned from 0.3 μs to 3 μs (a remarkable 10x increase) with a relatively small penalty in on-resistance, no leakage increase, no threshold voltage degradation and no reliability degradation. The gate driver has desaturation detection (DESAT) and soft shutdown circuitry to achieve a fast protection response of 800 ns with high noise immunity greater than 100 V/ns. The combination of GaN power devices with SCCL and a commercial gate driver with fastDESAT and high noise immunity allows short-circuit protection and fail-safe operation of GaN power electronics for additional robustness in motor drive applications.

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The Relevance of Trapped Charge for Leakage and Random Telegraph Noise Phenomena

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