United States

Hafnium oxide-based ferroelectric tunnel junctions (FTJs) are novel nonvolatile memory devices with promising advantages such as non-destructive readout in comparison with conventional ferroelectric random access memories. Reliability aspects of FTJ devices need to be investigated, including endurance, retention, ferroelectric switching, breakdown characteristics, and memory window. These characteristics exhibit promising results at room temperature; however, further analysis is required at different operating temperatures. In this work, we demonstrate the FTJ device characteristics at different temperatures varying from -40 °C to 60 °C.

IRPS 2022 Main Conference 

Impact of Temperature on Reliability of MFIS HZO-based Ferroelectric Tunnel Junctions

**[DOWNLOAD THE DRC 2021 DIGEST](https://drive.google.com/file/d/17_-pkYf4IBbVuNYgohTf0iZJORVGp_uN/view?usp=sharing)**

**[DOWNLOAD A COPY OF THE FINAL DRC PROGRAM](https://drive.google.com/file/d/1Ek8UIDCowpLq0z2hXav5tn67FboxS03N/view?usp=sharing)**

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Given the ongoing global health concerns associated with COVID-19 (Coronavirus), the DRC leadership has decided to hold the 2021 Device Research Conference in a virtual (online) format. This follows an enormously successful 2020 DRC held virtually, in which we had record attendance and worldwide participation of more than 875 attendees from 33 countries.

The 2021 Conference will feature:

* Informative, timely short courses in rapidly developing fields
* Oral and poster presentations on electronic/photonic device experiments and simulations
* Plenary and invited presentations given by worldwide leaders
* Evening “rump” session
* Strong student participation and Student Paper Awards

DRC is held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 23-25. As has happened in person in past years, in 2021, the virtual DRC and EMC sessions on the shared day, Wednesday, June 23, will be open to all attendees from both conferences. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences. For information on the 63rd Electronic Materials Conference, please visit the [EMC 2021 website.](https://www.mrs.org/63rd-emc/)

2021 DRC individual presentation videos will become available in Underline at the end of each technical session. A recording of each full live session with Q&A will be posted later during the conference. To facilitate re-viewing of recorded talks and sessions, the DRC Underline site will remain open through 11:59pm (US EDT) on July 7th. DRC Conference registration will remain open at www.mrs.org/drc-2021/registration through June 30th.

Thank you for joining us at the 2021 Device Research Conference!

**General Chair**
 Zhihong Chen, Purdue University

**Technical Program Chair**
 Becky (R.L.) Peterson, University of Michigan

**Technical Program Vice-Chair**
 Gregg Jessen, BAE Systems

You can register for the 79th Device Research Conference with the following link. https://www.mrs.org/drc-2021

DRC 2021

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

poster

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

This paper presents a synthesized version of the silicon odometer aging sensor for measuring the frequency degradation caused by device degradation mechanisms in high volume semiconductor products. In the design, three ring oscillators (ROSCs) composed of inverter, NAND, and NOR gates are implemented in register-transfer-level (RTL), with the ability to be stressed in an AC or DC stress condition. The new odometer has product level features such as calibration-free operation, automatic frequency dead zone escape, and start-up glitch removal. The odometer verilog code was synthesized and automatically placed-and-routed in three different technologies using standard ASIC design tools. As a proof of concept, we show aging data collected from a 65nm test chip with 12 synthesized odometer instances.  

A Calibration - Free Synthesizable Odometer Featuring Automatic Frequency Dead Z one Escape and Start - up Glitch Removal

Time-Dependent Variability phenomena can have a considerable impact on circuit performance, especially for deeply-scaled technologies. To account for this, these phenomena need to be characterized and modelled. Such characterization is often performed at the device level first. Then, the model extracted from such characterization should be validated at the circuit level. To this end, this paper presents a novel chip fabricated in a 65-nm technology that contains an array of 6T SRAM cells. This chip includes some features that make it especially adequate for the characterization of the impact of Time-Dependent Variability phenomena. To demonstrate this adequacy, different tests have been performed to evaluate how Time-Dependent Variability phenomena impact several relevant performance metrics of SRAM cells.

A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies

The introduction of Ferroelectric Tunnel Junctions (FTJs) in embedded memory systems and in brain-inspired computing platforms requires a deeper understanding of their reliability and degradation mechanisms. Here we combine an extended stress/measure (DC I-V, PUND, C-f/G-f) set with a new FTJ small signal model, that specifically considers the physical properties and the role of each layer. Results reveal that reliability is ultimately limited by defect generation in the ferroelectric, in line with simulation on MFM devices. Asymmetry in the polarization-dependent leakage increase (due to defect generation) is found, that is associated with different stages (wake-up, fatigue, aging) of device lifetime.

Combining Experiments and a Novel Small Signal Model to Investigate the Degradation Mechanisms in Ferroelectric Tunnel Junctions

A novel Ferroelectric FET (FeFET) structure to enable multi-level cell (MLC) storage using a cleaved gate (CG) is proposed for the first time. The CG-FeFET’s gate is divided into two gates by an insulator. The CG-FeFET is optimized based on well-calibrated TCAD models. We perform an extensive design space exploration by evaluating: 1) the impact of the length of separation oxide (LOX) between source side gate (G_S) and drain side gate (G_D); 2) whether reading from G_S or G_D is better; 3) the best placement of the insulator between the two gates comparing symmetric (LG_S= LG_D) vs. asymmetric (LG_S≠LG_D) structure.  

Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage

We applied Monte Carlo (MC) aging simulation flow to explain measured aging effects of PUF (Physically Unclonable Function) circuit. Simulation data provides a good understanding of how PUF circuit might fail with the NBTI effect. The flow predicts updated design shows better reliability result. We demonstrated that NBTI variation model requires correct consideration of the MOSFET device size. 

Reliability Analysis of Physically Unclonable Function by Using Aging Variability Simulation

A constant current stress scheme is implemented for endurance study on OTS-PCM devices for the first time. It provides a feasible method to estimate the read/write endurance for cross-point PCM products, which can save testing time for chips qualification.          

Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme

Endurance ~ 1012 cycling of ferroelectric (FE) and antiferroelectric (AFE) HfZrO2 (HZO) capacitors are achieved experimentally by adjusting the programming pulse width (tp). The correlation between switching polarization (△P) and fatigue behavior of high endurance is discussed. For long tp (= 1 µs), AFE exhibits excellent endurance with &gt; 1010 cycles as compared with FE ~ 109 cycles. With shortening tP, the endurances of FE and AFE are significantly improved. There is no significant degradation until &gt; 1011 cycling is observed for FE with tp=20ns. 

Correlation between Access Polarization and High Endurance (~ 1012 cycling) of Ferroelectric and Anti-Ferroelectric HfZrO2

We propose an aging degradation suppression scheme at constant performance by controlling supply voltage and body bias for an FDSOI device. Reducing supply voltage while increasing body bias can maintain performance and suppress dynamic power and aging degradation caused by BTI. From measurement results of ring oscillators in a 65 nm    FDSOI, NBTI- and PBTI-induced degradations can be reduced by 29% and 10% at 1.5 V supply voltage and 0.15 V forward body bias paying the penalty of 2x leak power increase.

An Aging Degradation Suppression Scheme at Constant Performance by Controlling Supply Voltage and Body Bias in a 65 nm Fully-Depleted Silicon-On-Insulator Process

To enable high-density cross-point arrays of magnetic memory a suitable access device is necessary. A promising candidate for this role is a metal-semiconductor-metal (MSM) tunneling device. In this work, the operation of an ultrathin Pt\6nm a-IGZO\Pt stack as an MSM selector is discussed. The focus is given to understanding the breakdown mechanism at high current regime, which prevents it from reaching the target current density. The breakdown is preceded by a gradual degradation process, which is manifested as an increase in high-field current after prolonged stress. This effect is recoverable – current returns to original value after sufficient delay time. Based on these observations, we propose a mechanism, where increased high-field current can be explained as a decrease in Schottky barrier height arising from stress-induced increase in oxygen vacancies.

Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors

In this work, we demonstrate experimentally an RRAM-based IMC logic concept with strong resilience to RRAM variability, even after one million endurance cycles. Our work relies on a generalization of in-memory Scouting Logic, and we demonstrate it experimentally with up to 16 parallel devices, a new milestone for RRAM in-memory logic. Moreover, we combine IMC with a new smart Multi-Level-Cell (MLC) programming algorithm resilient to conductance relaxation and demonstrate experimentally, for the first time, an IMC RRAM-based MLC 2-bit adder.

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