United States

Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.

IRPS 2022 Main Conference 

Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators

physical modeling

deep neural network accelerators

rram

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

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**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

The leakage current and threshold voltage instability of NO nitrided SiC(1-100) m-face MOS devices was intensively studied. Nitridation at a typical temperature of 1250°C was found to reduce the onset field of Fowler-Nordheim tunneling current by about 1 MVcm-1. Moreover, systematic positive and negative voltage stress measurements revealed that the nitrided m-face MOS devices exhibit much larger threshold voltage shifts compared to a reference Si-face device. Despite the improvement in the MOS interface quality by NO nitridation, our results clearly indicate the drawbacks of nitridation for m-face MOS devices in terms of reliability.

Investigation of reliability of NO nitrided SiC(1-100) MOS devices

Threshold voltage instability in 4H-SiC MOSFETs was investigated by means of combined cyclic gate bias stress measurements and single gate bias point measurements. This allowed to separate the contributions of interface states (Nit) and near interface oxide traps (NIOTs) in the nitridated deposited gate oxides. Nanoscale chemical analyses by electron energy loss spectroscopy allowed to correlate these trapping states to the presence of a sub-stoichiometric silicon oxide (~1 nm) and carbon-related defects (&lt;1 nm) on different SiO2/4H-SiC interfaces In particular, the sub-stoichiometric silicon oxide was correlated to the interface states and the carbon-related defects have been correlated to the NIOTs.

SiO2/4H-SiC interfacial chemistry as origin of the threshold voltage instability in power MOSFETs

The circuit functionalities of Complementary Metal-Oxide-Semiconductor (CMOS) devices on 4H-SiC for digital and analog circuit applications beyond 200˚C have been extensively studied, however, the reliability of the devices on SiC needs to be demonstrated due to the traps at/near the dielectric interface. In this report, the reliability of n- and p- Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has been studied on three different gate oxide conditions – thick thermally grown, ultrathin thermal + thick CVD oxide and ultrathin thermal + thin CVD oxide in terms of their bias temperature instability (BTI) measurement. The MOSFETs were stressed at various constant bias voltages at 150˚C and up to 105s. The threshold voltage shift due to positive bias on n-MOSFET is &lt;0.5V after 105s at +25Vwhile p-MOSFET shows a larger shift of -1.9V shift after 105s at -25V and 150˚C for ultrathin + thick CVD oxide. The report also establishes improvement in reliability of p-MOSFETs with ultrathin + CVD oxides over thermally grown oxides.

Bias Temperature Instability on SiC n- and p-Channel MOSFETs for High Temperature CMOS Applications

In-memory computing (IMC) with memory arrays allows reducing the time and energy consumption for matrix vector multiplication (MVM) for artificial neural networks (ANN) inference. However, the IMC accuracy is affected by nonidealities, such as program/read variations of device conductance and the parasitic voltage (IR) drop along the wires, whose impact quickly increases when increasing the array size. This work presents new IMC circuit architectures for mitigating both variations and IR drop at the same time. The  new schemes allow for improving the accuracy of an ANN from 72.7% to 94.9%, compared to a software accuracy of 96.9%, at the expense of an increase of the memory array area.

Mitigating read-program variation and IR drop by circuit architecture in RRAM-based neural network accelerators

In this work, analog and RTN performance of transistors operating in low current conditions were investigated. It is proven that in subthreshold regime the RTN signal is driven by defects located at the STI edges. Reducing the amount of electrical impurities situated at the device periphery lead to evident RTN improvement without significant change in targeting or reliability, and reduce the noise sensitivity to temperature and body bias. Empirical correlation between RTN and intrinsic gain was also reported, which can be used for fast inline process monitoring of defects located in the STI edges.

Impact of Electrical Defects located at Transistor Periphery on Analog and RTN Device Performance

In this paper, we present a detailed study of negative bias temperature instability (NBTI) and Time dependent dielectric breakdown (TDDB) reliability in p-type stacked gate- all -around (GAA) Nanosheet (NS) transistors with SiGe channel and compared with NS Si pFETs. Robust NBTI and TDDB reliability performance is achieved on SiGe gate-all-around NS.


SiGe Gate-All-around Nanosheet Reliability

The issues related to the failure analysis of 4H-SiC PowerMOSFET failed at EWS (Electrical Wafer Sorting) such as the channel leakage current is investigated. In particular, EWS is carried out in the namely defect free wafers areas monitored at several inline levels. This paper reports on the electrical based methods used to spot macroscopic defects even if they are invisible at optical wafer inspections. In particular, the current separation technique on source and gate terminals allowed to reduce the number of  candidate samples to be investigated

Failure analysis addressing method of optically undetected defectivity on 4H-SiC PowerMOSFET epitaxial layer

This work presents the influence of SiC epitaxial wafer quality on yield of SiC-DMOSFETs. Various wafer quality indicators were estimated by an integrated wafer quality evaluation system. SiC-DMOSFETs were fabricated on six 100 mm 4H-SiC epitaxial wafers. We show that the yield of SiC-DMOSFETs is related to threading screw dislocation density, defect density and bunched-steps length density evaluated by wafer inspection apparatuses.

Influence of SiC epitaxial wafer quality on yield of 1.2kV SiC-DMOSFETs

Several designs of 1.2kV-rated 4H-SiC PiN diodes and Junction Barrier Schottky (JBS) diodes have been successfully fabricated with various P+ implantation conditions resulting in different junction profiles. P+ regions were implanted at both room temperature and elevated temperature in order to monitor the generation of Basal Plane Dislocations (BPDs) and study their impact on device long term reliability. It was found that, when the dose in the deeper portion of the junction (implemented by high energy) is well suppressed, static and long-term reliability performances of room temperature implanted devices can be maintained similar to those of high temperature implanted devices.

Static Performance and Reliability of 4H-SiC Diodes with P+ Regions Formed by Various Profiles and Temperatures

Resistive random-access memory (RRAM)-based in-memory computing (IMC) recently became a promising paradigm for efficient deep neural network acceleration. The multi-bit RRAM arrays provide dense storage and high throughput, whereas the physical non-ideality of the RRAM devices impairs the retention characteristics of the resistive cells, leading to accuracy degradation. On the algorithm side, various hardware-aware compression algorithms have been proposed to accelerate the computation of deep neural networks (DNNs) computation. However, most recent works individually consider the "model compression" and "hardware robustness". The impact of the RRAM non-ideality for the sparse model is still under-explored. In this work, we present a novel temperature-resilient RRAM-based IMC scheme for reliable DNN inference hardware. Based on the measurement from a 90nm RRAM prototype chip, we first explore the robustness of the sparse model under the different operating temperatures (25°Cto 85°C). On top of that, we propose a novel robustness-aware pruning algorithm, then further enhance the model robustness with a novel sparsity-aware noise-injected fine-tuning. The proposed scheme achieves &gt;92% CIFAR-10 inference accuracy after one-day operation, which is &gt;37% higher than the state-of-art method.

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Investigation of reliability of NO nitrided SiC(1-100) MOS devices

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Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference