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Software transactional memory (STM) is a synchronization paradigm originally proposed for throughput-oriented computing to facilitate producing performant concurrent code that is free of synchronization bugs. With STM, programmers merely annotate code sections requiring synchronization; the underlying STM framework automatically resolves how synchronization is done. Today, the programming issues that motivated STM are becoming a concern in embedded computing, where ever more sophisticated systems are being produced that require highly parallel implementations. In this area, an evolution is underway to produce sophisticated systems such as autonomous vehicles that require highly parallel implementations. These implementations are often produced by engineers and control experts who may not be well versed in concurrency-related issues. In this context, a real-time STM framework would be useful in ensuring that the synchronization aspects of a system pass real-time certification. However, all prior STM approaches fundamentally rely on retries to resolve conflicts, and such retries can yield high worst-case synchronization costs compared to lock-based approaches. Unfortunately, prior work on real-time STM is not helpful in this regard because it has been limited to approaches that retry conflicting transactions; such approaches require retry bounds, which can be large and pessimistic on multiprocessors. This paper presents a new STM class called Retry-Free Real-Time STM (R^2STM), which is designed for worst-case real-time performance. The benefit of a retry-free approach for use in a real-time system is demonstrated by a schedulability study, in which it improved overall schedulability across all considered task systems by an average of 95.3% over a retry-based approach. This paper also presents TORTIS, the first R^2STM implementation for real-time systems.

IEEE RTSS 2021

TORTIS: Retry-Free Software Transactional Memory for Real-Time Systems

software transactional memory

transactional memory

throughput

embedded computing

concurrent computing

codes

costs

real time

programming

real-time systems

 **RTSS 2021** has successfully concluded. Hope you have enjoyed it, and look forward to seeing you next year in person.
    Announcement for the Awards:
 * Best Paper Award goes to: Monte Carlo Response-Time Analysis, Sergey Bozhko, Georg von der Brüggen, and Björn Brandenburg
 * Best Student Paper Award goes to: Automatic Energy-Hotspot Detection and Elimination in Real-Time Deeply Embedded Systems, Mohsen Shekarisaz, Lothar Thiele, and Mehdi Kargahi.
 * Best Solution Award for Industry Session goes to: Toward Real-Time Guaranteed Scheduling for Autonomous Driving Systems. Jinghao Sun, Tianyi Wang, Kailu Duan, Bin Lu, Jiankang Ren, Zhishan Guo, and Guozhen Tan.



The IEEE Real-Time Systems Symposium (RTSS) is the premier conference in the field of real-time systems, and is a venue for researchers and practitioners to showcase innovations covering all aspects of real-time systems, including theory, design, analysis, implementation, evaluation, and experience. 

technical paper

Real-time applications with high computational demand, e.g., autonomous driving, are emerging and their complex nature conforms to a DAG(directed acyclic graph) structure. We propose a conditionally optimal parallelization for real-time DAG tasks for global EDF, ensuring complete execution of all tasks within the deadline. To achieve this, we formalize a monotonic increasing property of both tolerance and interference to the parallelization option. Using such properties, we develop a unidirectional search algorithm that can assign parallelization options in polynomial time, which we formally prove the optimality. We observe significant improvement of schedulability through simulation experiment, and then in the following implementation experiment, we demonstrate that the algorithm is practically applicable for real-world use-cases.

Conditionally Optimal Parallelization of Real-Time DAG Tasks for Global EDF

Even though earliest-deadline-first (EDF) is optimal in terms of uniprocessor schedulability, it is co-NP-hard to precisely verify uniprocessor schedulability for constraineddeadline task sets. The most efficient way to solve this problem in polynomial time is via a partially linear approximation of the demand bound function. Such approximation leads to a simple uniprocessor schedulability testing with speedup factor ρ. Such a result further leads to Deadline-Monotonic Partitioned-EDF on multi-processors with speedup factor of 1 + ρ − 1/m (where m is the number of processors). The current state of the art results indicate that ρ is within the range [1.5, 14/9]. Especially, it has been a conjecture that ρ = 1.5. This paper improves the range of ρ to (1.5026, 1.5380). The improved lower bound disproves the conjecture of lower bound 1.5. A novel technique is to construct an auxiliary function that is larger than the approximate demand bound function but keeps the supremum ρ unchanged. It solves the dilemma that beating the lower bound 1.5 requires extremely large task sets, while the large size makes it difficult to check the schedulability. This technique not only enables us to disprove 1.5 by a task set of only eight tasks, but also sheds light on future work in transferring/downsizing task sets and deriving utilization bound based tests for various workload abstraction models, such as DAG tasks.

Tighter Bounds of Speedup Factor of Partitioned EDF for Constrained-Deadline Sporadic Tasks

Prior algorithms that have been proposed for the uniprocessor scheduling of systems of elastic real-time tasks have computational complexity quadratic (O(n^2)) in the number of tasks n, for both initialization and for admitting new tasks during run-time. In our work-already-published [1], we present a more efficient implementation in which initialization takes quasilinear (O(n log n)), and on-line admission control, linear (O(n)), time.

Linear-time admission control for elastic scheduling

In this paper, we report on the ongoing development of POET, the first foundational and automated response-time analysis tool. The certificates produced by POET are short, readable, and fully commented Coq files that can be machine-checked in (usually) minutes. Moreover, we describe the mechanisms implemented in POET to ensure the validity of the generated certificates. Finally, we report on a preliminary evaluation of the effectiveness and practicality of our approach on synthetic task sets.

Automatically Generated Response-Time Proofs as Evidence of Timeliness

Numerical simulations often play an important role when evaluating and comparing the performance of schedulability tests, as they allow to empirically demonstrate their applicability using synthesized task sets under various configurations. In order to provide a fair comparison of various schedulability tests, von der Brüggen et al. presented the first version of an evaluation framework for self-suspending task sets. In this work-in-progress, we further enhance the framework by providing more features to ease the use, e.g., Python 3 support, an improved GUI, multiprocessing, Gurobi optimization, and external task evaluation. In addition, we integrate the state-of-the-arts we are aware of into the framework. Moreover, the documentation is improved significantly to simplify the application in further research and development. To the best of our knowledge, the framework contains all suspension-aware schedulability tests for uniprocessor systems and we aim to keep it up-to-date.

Evaluation Framework for Self-Suspending Schedulability Tests

The temporal correctness of safety-critical systems is typically guaranteed via a response-time analysis (RTA). However, as the systems become complex (e.g., parallel tasks running on a multicore platform), most existing RTAs either become pessimistic or do not scale with respect to e.g., the number of tasks or period values. To make a trade-off between accuracy and scalability, recently, a new reachability-based RTA called schedule-abstraction graph (SAG) has been introduced by Nasri et al. It explores the space of possible decisions that a scheduling policy can take while dispatching a set of tasks or jobs on processing resources. The analysis is at least three orders of magnitude faster than other exact RTAs and is able to identify many more schedulable task sets than the existing fixed-point iteration-based analyses. One fundamental limitation of the SAG analysis is that in its reachability graph, each edge can only account for a single scheduling decision. Therefore, the graph grows exponentially when there are large uncertainties in the release time or execution time of the jobs. In this paper, we improve the scalability of the SAG analysis by introducing partial-order reduction (POR) rules that allow combining multiple scheduling decisions on one edge and hence avoiding combinatorial exploration of all possible scheduling decisions. An empirical evaluation shows that our solution is able to reduce the runtime by five orders of magnitude and the number of explored states by 98%.

Partial-Order Reduction in Reachability-based Response-Time Analyses

Measurement-based WCET methods are reliable as long as we know all the application behaviors at design-time. In particular, we need to observe all the possible execution time behaviors before the actual system run-time to get a reliable estimation. This is, unfortunately, difficult to achieve. In this work, we propose an online monitoring framework with the goal to detect, at run-time, unexpected application behaviors and trigger the probabilistic-WCET re-estimation when needed. The online monitoring and estimation framework allows dealing with unexpected situations, such as never-seen applications, faults, or incorrect offline estimations. The proposed approach is tested with simulated and real data.

Run-time pWCET estimation and quality monitoring

Intersections are critical elements of urban traffic management and are identified as bottlenecks prone to traffic congestion and accidents. Intelligent intersection management plays a significant role in improving traffic efficiency and safety determining, among other metrics, the waiting time that vehicles incur when crossing an intersection. This work presents a preliminary analysis of the worst-case response time of intersection management protocols that handle mixed traffic with autonomous and human-driven vehicles. We deduce theoretical bounds for such time considered as the interval between the injection of a vehicle in the road system and its departure from the intersection, considering different intersection management protocols for mixed traffic, namely the Synchronous Intersection Management Protocol (SIMP) and several configurations of the conventional Round-Robin (RR) policy. Simulation results validate the analytical bounds partially. Ongoing work addresses the queue dynamics and its reliable detection by traffic simulators.

Worst-Case Response Time of Intersection Management Protocols

In this paper, we propose to use Schedule Abstraction Graphs (SAGs) to determine exact worst-case latency of packets at an egress port of an Ethernet TSN switch with Time-aware Shapers (TASs). We briefly sketch how to apply the existing SAG framework in a TSN context and extend the framework with FIFO-queues and TASs.

Analysis of TSN Time-aware Shapers using Schedule Abstraction Graphs

This work will demonstrate a new flavor of the RA-TDMA set of protocols, namely RA-TDMAs+, which uses IEEE-802.11 (WiFi) COTS hardware in ad-hoc mode to set up a dynamic mesh network of mobile nodes with high-bandwidth. The protocol uses topology tracking to configure the TDMA frame and robust relative synchronization to define the TDMA slots without resorting to a global clock and in the presence of interfering traffic. The demo will set up a small-scale testbed using COTS hardware, thus evidencing the feasibility of the approach, and it will show “live plots” of the temporal (synchronization) and topological views of the network.

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