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The use of wide bandgap (WBG) devices in the dominant voltage-source inverters (VSIs) creates more challenging conducted common-mode (CM) electromagnetic interference (EMI) issues. Traditional way of suppressing CM EMI is by adding external filters. However, the added filter can add significant mass and volume to the inverter. The use of existing current-source inverter (CSI) can help relieve the CM EMI issue, but WBG-CSI’s EMI profile still exceeds EMI standards. In this paper, two new balanced current-source inverter (CSI) topologies are proposed that provide several advantages over the standard VSIs or existing CSI topology when using WBG power switches. For both balanced CSI topologies, the use of additional three switches generate a second common-mode voltage (V_cm) component that forces the total V_cm of both inverters to be close to zero. This significantly reduces the inverters’ conducted CM EMI. Moreover, the proposed H10-Balanced-CSI topology combined with its modulation scheme make its CMV cancellation insensitive to propagational delay distortions among its switches.

IEEE WiPDA 2021

A Balanced Current-Source Inverter and its dc-Link Shunted Variant for Common-Mode Voltage Cancellation

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

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The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

poster

Gallium Nitride (GaN) vertical n-p-n 3D nanostructured transistors have been demonstrated to be excellent normally OFF devices, making them exploitable for next generation power converters. However, their stability is still under investigation. 
The aim of this work is to present one of the first studies on the performance and stability of n-p-n vertical FinFETs, to contribute to the understanding of the related physics. Devices show positive threshold voltage of 3 V, that was found to be affected by positive bias temperature instability. The analysis conducted reveals the presence of a trapping process with activation energy of 0.30 eV, which is ascribed to defects at the semiconductor-oxide interface. Capacitance-voltage measurements and TCAD simulations were used to gather further information on trapping phenomena and device’s working behavior.


Dynamic and Capacitive Characterization of 3D GaN n-p-n Vertical Fin-FETs

Vertical GaN-based devices offer the possibility to overcome several limitations of lateral high-electron mobility transistors (HEMTs). Since the electric field peaks in vertical transistors occur within the bulk instead of the surface, they are expected to be less susceptible to trapping and the associated reduction in dynamic performance. 
In this presentation, the deep-level trapping behavior of GaN-on-GaN current aperture vertical electron transistors (CAVETs) is characterized by means of current transient measurements and compared to AlGaN/GaN HEMTs fabricated on the same substrate.

Deep-level characterization of GaN-on-GaN current aperture vertical electron transistors

Effective mobility in GaN recess-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with Al1-xSixO gate dielectric layers and AlN mobility enhancement layers is reported. Devices with AlN/Al0.23Si0.77O gate dielectric show maximum mobility of over 1000 cm2V-1s-1 at room temperature, rising to ~2800 cm2V-1s-1 at 200°C, whilst maintaining normally-off operation. Mobility is linked to scattering mechanisms associated with carrier density profiles in the channel.

High mobility in GaN MOSFETs with AlSiO gate dielectric and AlN mobility enhancement layer

This work provides the first demonstration of vertical GaN Junction Barrier Schottky (JBS) rectifiers fabricated by etch and regrowth of p-GaN. A reverse blocking voltage near 1500 V was achieved at ~ 1 mA reverse leakage, with a sub 1 V turn-on and a specific on-resistance of 10 mOhm-cm2. This result is compared to other reported JBS devices in the literature and our device demonstrates the lowest leakage slope at high reverse bias. A large initial leakage current is present near zero-bias which is attributed to a combination of inadequate etch-damage removal and passivation induced leakage current.

Etched and Regrown Vertical GaN Junction Barrier Schottky Diodes

The work presented in this paper investigates the switching behavior of the power semiconductors at a hybrid Si/SiC ANPC circuit, where the Si IGBTs switch at line frequency while the SiC MOSFETs switch at PWM frequency. In particular, this work quantifies the impact of the forward recovery voltage (FRV) originated in the bipolar devices, i.e., IGBTs and freewheeling diodes, during the transition from non- to full-conduction. Such transition being originated by the on/off commutation of the SiC devices. The obtained experimental results also show the impact of various operational and environmental factors on the FRV magnitude and evolution. The evaluation done indicates that FRV effects must be taken into account both in terms of power loss dissipation and voltage overshoots when using hybrid Si/SiC ANPC topology.

Switching behavior of a hybrid Si-IGBT and SiC MOSFET based ANPC Topology

In this presentation, an intelligent gate driver for parallel-connected SiC MOSFETs is presented. Commercial gate drivers often slow down the switching event to compensate for unevenly distributed switching losses in parallel-connected MOSFETs. With the use of the presented gate driver, it is possible to match the temperature of parallel-connected MOSFETs even with low gate resistances. To achieve this, the gate signals of the parallel-connected MOSFETs are delayed in the nano second range in order to influence the current distribution during the switching events. This allows fast switching operations without the need for derating the switching cell. The measurement results are compared with a push-pull gate driver. It is shown that the temperature difference of two MOSFETs connected in parallel can be reduced from 8 K when using a push-pull gate driver to 0 K when using the presented gate driver. The gate driver thus makes it possible to fully exploit the potential of SiC MOSFETs and to increase the power density of power electronics converters.

Balancing Unequal Temperature Distributions of Parallel-Connected SiC MOSFETs Using an Intelligent Gate Driver

Silicon carbide (SiC) power devices operate at high switching frequencies with high voltages and good stabilities owing to their advantages in excellent breakdown field strength, heat dissipation characteristics, and electron saturation velocity, and so on. Therefore, SiC-based systems can achieve a high power density compared to conventional Si-based systems. However, high dv/dt and di/dt accompanied with high-speed switching operations can cause EMI noise issues. Traditional gate drivers cannot actively control such EMI noise problems. This digest proposes an integrated active gate driver (AGD) to solve the noise issues. The proposed AGD controls the switching speed through controllable AGD voltages in real-time according to the system feedbacks such as the DC-link voltage, output current, and device temperature. The proposed AGD enables switching devices to control the switching speed accurately under various system operational conditions. Simulation and experimental results are presented to verify the proposed method.

An Integrated Active Gate Driver for SiC MOSFETs

This presentation shows a liquid metal-based cooling system for power converters with an inductor integrated magnetohydrodynamic (MHD) pump. The inductor in this case not only functions as the pump for liquid metal but also can be an essential part of typical power converters such as the output inductor of a buck converter. Two prototypes of liquid metal-based cooling systems were designed and built. The first prototype is an MHD pump with an external current source and permanent magnets and to evaluate the effectiveness and power consumption of liquid metal-based cooling. The second prototype for the first time integrates the MHD pump into an inductor, which eliminates the need for an external power supply and permanent magnets. Since the inductor is part of the power converter to be cooled, the flow rate can be self-adjusted with the load condition. Simulation and experimental results validate the concept of the inductor integrated liquid metal pump and demonstrate the advantage of the liquid metal cooling system over non-metallic fluid-based liquid cooling systems in terms of power density, cooling efficiency, power consumption, reduction of rotatory components, and lowered acoustic noise.

Liquid Metal based Cooling for Power Electronics Systems with Inductor Integrated Magnetohydrodynamic Pump (MHD Pump)

In this work, electrical parameters of silicon carbide MOSFETs and their temperature dependency, as well as their electrical behavior over time are investigated. An approach is presented to make assertions about the condition of the
transistors during operation through the measurement of multiple temperature and degradation-sensitive electrical parameters. The on-state voltage, peak gate current and quasi-threshold voltage are monitored through dedicated acquisition circuits. An exemplary AC power cycling setup which combines switching and conduction losses while applying nominal DC-link voltage is used to characterize the parameters in operation. The setup consists of two half-bridge modules with measurement circuitry connected directly to the devices under test. Results show the capability
of the proposed circuits to measure parameters carrying temperature and health information in normal operation. A high linearity of the quasi-threshold voltage in regards to the junction temperature is found, with a relative temperature sensitivity in the per mille range, comparable to the sensitivity of the on-state resistance. No significant temperature sensitivity is found for the peak gate current, due to the specific gate driver design.

Characterization of Electrical Parameters for Health Monitoring in SiC MOSFETs During AC Power Cycling

LLC converters are the most popular isolated dc/dc converter with high efficiency power conversion and simple control strategy. To facilitate the designand optimization of LLC converters, in this article, we investigate the circuit and power loss models. The high accuracy of the circuit and power loss models are ensured by adopting time domain modelling. The power loss model is developed solely based on the manufacture provided datasheets with convenient yet effective evaluation of components performances. A simulation and design tool is built to further facilitate the evaluation of the LLC converters. Experimental results from a 500 W symmetric half-bridge LLC converter are presented and compared with the theoretical analysis results to validate the accuracy and effectiveness of the developed models.

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Next from IEEE WiPDA 2021

Dynamic and Capacitive Characterization of 3D GaN n-p-n Vertical Fin-FETs

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