United States

In this presentation, an intelligent gate driver for parallel-connected SiC MOSFETs is presented. Commercial gate drivers often slow down the switching event to compensate for unevenly distributed switching losses in parallel-connected MOSFETs. With the use of the presented gate driver, it is possible to match the temperature of parallel-connected MOSFETs even with low gate resistances. To achieve this, the gate signals of the parallel-connected MOSFETs are delayed in the nano second range in order to influence the current distribution during the switching events. This allows fast switching operations without the need for derating the switching cell. The measurement results are compared with a push-pull gate driver. It is shown that the temperature difference of two MOSFETs connected in parallel can be reduced from 8 K when using a push-pull gate driver to 0 K when using the presented gate driver. The gate driver thus makes it possible to fully exploit the potential of SiC MOSFETs and to increase the power density of power electronics converters.

IEEE WiPDA 2021

Balancing Unequal Temperature Distributions of Parallel-Connected SiC MOSFETs Using an Intelligent Gate Driver

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

[![](https://assets.underline.io/uploads/markdown_image/1/image/c8e1b0a2881d3bb0a75ece4761f43c9f.png)](https://drive.google.com/drive/folders/1GWEFLzH6K4aUBaJiBFJDw4x9sKLTl6-g?usp=sharing)


This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

technical paper

Transphorm Inc. is supplying N-polar GaN epitaxial wafers for ultra-high-performance RF and mm-wave electronics on sapphire and silicon carbide (SiC) substrates. In this work, we report on the manufacturing facility, epitaxial growth on
both 100-mm sapphire and 100-mm SiC, and device electrical performance. Results show good material quality, a low 2DEG sheet resistance with good uniformity, and good dynamic behavior with no current dispersion at 60 V at both room temperature and high temperature (150°C).

Commercially Available N-Polar GaN HEMT Epitaxy for RF Applications

The electrical measurements, performed on devices under test, showed a high ∆Vth between the Id/Vg curves at different Vd and a high ∆Ig; therefore, we started a simulation study in order to understand which physical parameters impact the drain current in subthreshold condition and consequently the gate current. One of these parameters turned out to be the traps concentration inside buffer layer and therefore the role of epitaxy in the active part of the device. Technology-Computer Aided Design (T-CAD) numerical simulations have been carried out, taking into account the tunneling effect under the Schottky gate. Different traps concentrations were investigated, and this analysis gives a good starting point for the epitaxy optimization especially linked to active part of the device.

T-CAD simulations study on drain leakage current and its correlation with gate current for AlGaN/GaN HEMTs

In this paper, the design method of Ka-band monolithic integrated circuit (MMIC) Doherty power amplifier (DPA) for 5G wireless communication based on a novel complex load modulation is demonstrated by using Cree’s 0.15 μm Gallium Nitride (GaN) on silicon carbide (SiC) process. Previously, the classical load modulation of DPA relies on the real-to-real transformation of carrier PA output impedance (RL to 2RL) from back off to saturation, and the value of RL is normally related with the input impedance of the employed impedance transformer (IT), which leads to the relatively low RL thus limiting the back-off efficiency of DPA. By using a novel complex load modulation, the RL is not limited by the used IT anymore, which results in the carrier PA can operate with higher output impedance. Consequently, higher back-off efficiency can be obtained. To verify the effectiveness of the design method, a GaN on SiC DPA was designed for 5G applications in a simulation environment. Simulated results of the proposed DPA exhibit drain efficiencies of 37.5% at 6 dB back-off point and 45.5% at the saturation from 26 GHz to 29 GHz.

Design of Ka-Band Doherty Power Amplifier Using 0.15 μm GaN on SiC Process Based on Novel Complex Load Modulation

Gallium Oxide (Ga2O3) is an emerging semiconductor for next-generation power electronics. In this context, the β-Ga2O3 film has been deposited on Si (100) substrate using pulsed laser deposition. XRD pattern of the deposited film shows the single crystalline nature with β-phase of Ga2O3. FESEM results confirm the film surface is smooth and uniform. Fabricated Schottky barrier diodes (SBDs) show good device performance with significantly high breakdown voltage and low ideality factor. Baliga’s figure of merit (V2BR/RON) has been computed to be 0.021 MWcm-2. The present research has evaluated the feasibility of cost-effective integration of β-Ga2O3 with well-established technology Si and it would provide a new research opportunity of β-Ga2O3 on Si with potential commercial applications as well as challenges to overcome for high-performance power devices soon.


Commercially Available N-polar GaN HEMT Epitaxy for RF Applications

This study analyzes the ability of various processing techniques to reduce leakage current in vertical GaN MOS devices. Careful analysis is required to determine suitable gate materials in GaN MOSFETs since they are largely responsible for determination of threshold voltage, gate leakage reduction, and number of interface traps. SiO2, Al2O3, and HfO2 films were deposited by atomic layer deposition and subjected to treatments nominally identical to those seen in vertical GaN MOSFET fabrication. This work determines mechanisms for reducing gate leakage by reduction of surface contaminants and interface traps using pre-deposition cleans, elevated temperature depositions, and post-deposition anneals. Al2O3 is an ideal candidate for a MOSFET gate dielectric with a breakdown electric field near 802 MV/cm which is an improvement on other reported breakdown strengths for similar films. SiO2 films treated with an 850 C anneal for 30 minutes show significant reduction in leakage current densities while maintaining breakdown at 5.4 MV/cm. HfO2 films show higher sensitivity to high temperature annealing suggesting more research into surface cleans is necessary prior to incorporation into a vertical GaN MOSFET process.

Analysis of ALD Dielectric Leakage in Bulk GaN MOS Devices

Gallium Nitride (GaN) vertical n-p-n 3D nanostructured transistors have been demonstrated to be excellent normally OFF devices, making them exploitable for next generation power converters. However, their stability is still under investigation. 
The aim of this work is to present one of the first studies on the performance and stability of n-p-n vertical FinFETs, to contribute to the understanding of the related physics. Devices show positive threshold voltage of 3 V, that was found to be affected by positive bias temperature instability. The analysis conducted reveals the presence of a trapping process with activation energy of 0.30 eV, which is ascribed to defects at the semiconductor-oxide interface. Capacitance-voltage measurements and TCAD simulations were used to gather further information on trapping phenomena and device’s working behavior.


Dynamic and Capacitive Characterization of 3D GaN n-p-n Vertical Fin-FETs

Vertical GaN-based devices offer the possibility to overcome several limitations of lateral high-electron mobility transistors (HEMTs). Since the electric field peaks in vertical transistors occur within the bulk instead of the surface, they are expected to be less susceptible to trapping and the associated reduction in dynamic performance. 
In this presentation, the deep-level trapping behavior of GaN-on-GaN current aperture vertical electron transistors (CAVETs) is characterized by means of current transient measurements and compared to AlGaN/GaN HEMTs fabricated on the same substrate.

Deep-level characterization of GaN-on-GaN current aperture vertical electron transistors

Effective mobility in GaN recess-gate metal-oxide-semiconductor field-effect transistors (MOSFETs) with Al1-xSixO gate dielectric layers and AlN mobility enhancement layers is reported. Devices with AlN/Al0.23Si0.77O gate dielectric show maximum mobility of over 1000 cm2V-1s-1 at room temperature, rising to ~2800 cm2V-1s-1 at 200°C, whilst maintaining normally-off operation. Mobility is linked to scattering mechanisms associated with carrier density profiles in the channel.

High mobility in GaN MOSFETs with AlSiO gate dielectric and AlN mobility enhancement layer

This work provides the first demonstration of vertical GaN Junction Barrier Schottky (JBS) rectifiers fabricated by etch and regrowth of p-GaN. A reverse blocking voltage near 1500 V was achieved at ~ 1 mA reverse leakage, with a sub 1 V turn-on and a specific on-resistance of 10 mOhm-cm2. This result is compared to other reported JBS devices in the literature and our device demonstrates the lowest leakage slope at high reverse bias. A large initial leakage current is present near zero-bias which is attributed to a combination of inadequate etch-damage removal and passivation induced leakage current.

Etched and Regrown Vertical GaN Junction Barrier Schottky Diodes

The work presented in this paper investigates the switching behavior of the power semiconductors at a hybrid Si/SiC ANPC circuit, where the Si IGBTs switch at line frequency while the SiC MOSFETs switch at PWM frequency. In particular, this work quantifies the impact of the forward recovery voltage (FRV) originated in the bipolar devices, i.e., IGBTs and freewheeling diodes, during the transition from non- to full-conduction. Such transition being originated by the on/off commutation of the SiC devices. The obtained experimental results also show the impact of various operational and environmental factors on the FRV magnitude and evolution. The evaluation done indicates that FRV effects must be taken into account both in terms of power loss dissipation and voltage overshoots when using hybrid Si/SiC ANPC topology.

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