United States

Vertical GaN-based devices offer the possibility to overcome several limitations of lateral high-electron mobility transistors (HEMTs). Since the electric field peaks in vertical transistors occur within the bulk instead of the surface, they are expected to be less susceptible to trapping and the associated reduction in dynamic performance. 
In this presentation, the deep-level trapping behavior of GaN-on-GaN current aperture vertical electron transistors (CAVETs) is characterized by means of current transient measurements and compared to AlGaN/GaN HEMTs fabricated on the same substrate.

IEEE WiPDA 2021

Deep-level characterization of GaN-on-GaN current aperture vertical electron transistors

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

[![](https://assets.underline.io/uploads/markdown_image/1/image/c8e1b0a2881d3bb0a75ece4761f43c9f.png)](https://drive.google.com/drive/folders/1GWEFLzH6K4aUBaJiBFJDw4x9sKLTl6-g?usp=sharing)


This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

technical paper

We investigate the influence of trap filling conditions on the extraction of the emission time constant (τ) of deep levels associated with Fe doping in AlGaN/GaN HEMTs. To this end, we monitor the drain current transients (DCTs) after a short (1 µs) trap filling pulse and investigate the effect of varying (i) gate voltage (VGS,fill) and (ii) drain voltage (VDS,fill) applied during the filling pulse. We find that the extracted τ weakly depends on VGS,fill and it decreases for VDS,fill below 40 V; instead, for VDS,fill > 40 V τ saturates to a value corresponding to the inverse of the emission rate (1/en) at room temperature. The decrease of τ with decreasing VDS,fill was explained with the aid of numerical simulations, by attributing it to the concurrent effect of both emission and capture processes during DCT. This dependence must be taken into account when using DCT to characterize trap emission dynamics in order to correctly estimate the capture cross-section from Arrhenius plots.

Effect of Trap-Filling Bias on the Extraction of the Time Constant of Drain Current Transients in AlGaN/GaN HEMTs

Low temperature power electronics is beneficialin many different applications. Wide band gap (WBG) devices are becoming increasingly popular due to their high performances over the traditional silicon (Si) technology. Different from the gallium nitride (GaN) enhancement mode (E-mode) device, the cascode GaN is composed of a low voltage Si MOSFET and a depletion mode GaN. The advantages of the cascode GaN over E-mode GaN are: 1) easy of drive; 2) high noise immunity. In this article, the cryogenic evaluation results, including both static and dynamic characterizations, for a state-of-the-art high performance 650 V GaNcascode field-effect transistor (FET) are presented and analyzed. The evaluated 650 V cascode GaN FET has better performance under cryogenic temperatures, like low on-state resistance, large threshold volatge, reduced switching times and switching losses. Comparison resultswith the 650 V E-mode GaN device are made, the results demonstrate that the cascode GaN would be more reliable due to the high threshold voltage.

Evaluation of the High Performance 650 V Cascode GaN FET under Low Temperature

Abstract— In this work, the humidity performance of three enhancement mode GaN HEMTs with different chip designs and packages from different manufacturers were investigated by a High Humidity, High Temperature, Reverse Bias (H³TRB) test. The devices were tested until end of life (EoL) with a few devices even surviving the end of the test after passing 6000 test hours. Some of the devices provided a precursor of the catastrophic failure, while others just failed suddenly. There were little changes in the characteristics obtained at intermediate measurements. The Weibull analysis of the failures shows a consistent and clear wear-out behaviour. These results document an excellent humidity capability of the tested GaN devices even outperforming usual silicon devices, although GaN devices exhibit smaller insulation distances and higher electric fields. However, during the initial phase of the test conductive anodic filaments (CAF) formed in the PCB adapters and compromised the leakage current readings such that the adapters had to be removed to be able to continue the test. In other words, the weakest spot is no longer the semiconductor device itself, but has moved to other components in the circuitry.

Humidity Capability of Enhancement Mode GaN High Electron Mobility Transistors

This paper provides the extra loss caused by
dynamic ON-Resistance in a soft-switching converter seeking to
incorporate it into the design process, studying its dependence on
temperature and switching frequency. Firstly, characterization
is conducted in double-pulse tests to verify some impact factors
which may vary in converter operation. Different operation
modes, hard-switching, soft-switching, and reverse conduction at
various temperatures, can be achieved using the full-bridge
schematics with an extra resistor. Secondly, a series resonant
converter is built based on the same testbed and an additional 16.8% conduction loss was observed in the worst case.

Dynamic ON-Resistance Characterization of GaN HEMT Under Soft-Switching Condition

Transphorm Inc. is supplying N-polar GaN epitaxial wafers for ultra-high-performance RF and mm-wave electronics on sapphire and silicon carbide (SiC) substrates. In this work, we report on the manufacturing facility, epitaxial growth on
both 100-mm sapphire and 100-mm SiC, and device electrical performance. Results show good material quality, a low 2DEG sheet resistance with good uniformity, and good dynamic behavior with no current dispersion at 60 V at both room temperature and high temperature (150°C).

Commercially Available N-Polar GaN HEMT Epitaxy for RF Applications

The electrical measurements, performed on devices under test, showed a high ∆Vth between the Id/Vg curves at different Vd and a high ∆Ig; therefore, we started a simulation study in order to understand which physical parameters impact the drain current in subthreshold condition and consequently the gate current. One of these parameters turned out to be the traps concentration inside buffer layer and therefore the role of epitaxy in the active part of the device. Technology-Computer Aided Design (T-CAD) numerical simulations have been carried out, taking into account the tunneling effect under the Schottky gate. Different traps concentrations were investigated, and this analysis gives a good starting point for the epitaxy optimization especially linked to active part of the device.

T-CAD simulations study on drain leakage current and its correlation with gate current for AlGaN/GaN HEMTs

In this paper, the design method of Ka-band monolithic integrated circuit (MMIC) Doherty power amplifier (DPA) for 5G wireless communication based on a novel complex load modulation is demonstrated by using Cree’s 0.15 μm Gallium Nitride (GaN) on silicon carbide (SiC) process. Previously, the classical load modulation of DPA relies on the real-to-real transformation of carrier PA output impedance (RL to 2RL) from back off to saturation, and the value of RL is normally related with the input impedance of the employed impedance transformer (IT), which leads to the relatively low RL thus limiting the back-off efficiency of DPA. By using a novel complex load modulation, the RL is not limited by the used IT anymore, which results in the carrier PA can operate with higher output impedance. Consequently, higher back-off efficiency can be obtained. To verify the effectiveness of the design method, a GaN on SiC DPA was designed for 5G applications in a simulation environment. Simulated results of the proposed DPA exhibit drain efficiencies of 37.5% at 6 dB back-off point and 45.5% at the saturation from 26 GHz to 29 GHz.

Design of Ka-Band Doherty Power Amplifier Using 0.15 μm GaN on SiC Process Based on Novel Complex Load Modulation

Gallium Oxide (Ga2O3) is an emerging semiconductor for next-generation power electronics. In this context, the β-Ga2O3 film has been deposited on Si (100) substrate using pulsed laser deposition. XRD pattern of the deposited film shows the single crystalline nature with β-phase of Ga2O3. FESEM results confirm the film surface is smooth and uniform. Fabricated Schottky barrier diodes (SBDs) show good device performance with significantly high breakdown voltage and low ideality factor. Baliga’s figure of merit (V2BR/RON) has been computed to be 0.021 MWcm-2. The present research has evaluated the feasibility of cost-effective integration of β-Ga2O3 with well-established technology Si and it would provide a new research opportunity of β-Ga2O3 on Si with potential commercial applications as well as challenges to overcome for high-performance power devices soon.


Commercially Available N-polar GaN HEMT Epitaxy for RF Applications

This study analyzes the ability of various processing techniques to reduce leakage current in vertical GaN MOS devices. Careful analysis is required to determine suitable gate materials in GaN MOSFETs since they are largely responsible for determination of threshold voltage, gate leakage reduction, and number of interface traps. SiO2, Al2O3, and HfO2 films were deposited by atomic layer deposition and subjected to treatments nominally identical to those seen in vertical GaN MOSFET fabrication. This work determines mechanisms for reducing gate leakage by reduction of surface contaminants and interface traps using pre-deposition cleans, elevated temperature depositions, and post-deposition anneals. Al2O3 is an ideal candidate for a MOSFET gate dielectric with a breakdown electric field near 802 MV/cm which is an improvement on other reported breakdown strengths for similar films. SiO2 films treated with an 850 C anneal for 30 minutes show significant reduction in leakage current densities while maintaining breakdown at 5.4 MV/cm. HfO2 films show higher sensitivity to high temperature annealing suggesting more research into surface cleans is necessary prior to incorporation into a vertical GaN MOSFET process.

Analysis of ALD Dielectric Leakage in Bulk GaN MOS Devices

Gallium Nitride (GaN) vertical n-p-n 3D nanostructured transistors have been demonstrated to be excellent normally OFF devices, making them exploitable for next generation power converters. However, their stability is still under investigation. 
The aim of this work is to present one of the first studies on the performance and stability of n-p-n vertical FinFETs, to contribute to the understanding of the related physics. Devices show positive threshold voltage of 3 V, that was found to be affected by positive bias temperature instability. The analysis conducted reveals the presence of a trapping process with activation energy of 0.30 eV, which is ascribed to defects at the semiconductor-oxide interface. Capacitance-voltage measurements and TCAD simulations were used to gather further information on trapping phenomena and device’s working behavior.


Downloads

Next from IEEE WiPDA 2021

Effect of Trap-Filling Bias on the Extraction of the Time Constant of Drain Current Transients in AlGaN/GaN HEMTs

Similar lecture

Increased 3rd Quadrant Current Handling Capability of 1.2kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances

.css-70qvj9{display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;}Downloads

Next from IEEE WiPDA 2021

Effect of Trap-Filling Bias on the Extraction of the Time Constant of Drain Current Transients in AlGaN/GaN HEMTs

Similar lecture

Increased 3rd Quadrant Current Handling Capability of 1.2kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances

Downloads