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The electrical measurements, performed on devices under test, showed a high ∆Vth between the Id/Vg curves at different Vd and a high ∆Ig; therefore, we started a simulation study in order to understand which physical parameters impact the drain current in subthreshold condition and consequently the gate current. One of these parameters turned out to be the traps concentration inside buffer layer and therefore the role of epitaxy in the active part of the device. Technology-Computer Aided Design (T-CAD) numerical simulations have been carried out, taking into account the tunneling effect under the Schottky gate. Different traps concentrations were investigated, and this analysis gives a good starting point for the epitaxy optimization especially linked to active part of the device.

IEEE WiPDA 2021

T-CAD simulations study on drain leakage current and its correlation with gate current for AlGaN/GaN HEMTs

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

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The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

poster

Wide bandgap devices in combination with TCM (for soft switching) are typically applied in inverters to achieve high power density and efficiency. This has the disadvantage of a huge current ripple during sinusoidal peak. DPWM counteracts this problem by avoiding switching actions in this section. Due to the rapidly changing voltage across the output capacitors, oscillations within the filter may occur when entering DPWM interval. This current peak can saturate the inductor and the output voltage is distorted as well. This paper proposes a method to mitigate these oscillations by bringing the capacitor voltages to the required voltage prior DPWM interval. Compared to conventional TCM modulation, lower losses result. By damping the oscillations induced by DPWM it is suitable for grid and motor applications.

Modulation Strategy Comprising TCM with Frequency Limit and DPWM for Fast Switching GaN-Inverters

With the demand for higher power and lighter charger/adapters significantly increasing, the application of GaN solutions in this space is equally growing. One of the GaN solutions is the Integrated Power Stage (IPS) which is based on a System in Package (SiP) concept that includes driver and GaN power switch. In contrast to GaN discrete solutions, GaN IPS is very attractive for ≥ 45W to ≤ 1kW power supply applications as it further reduces the converter size, Bill Of Material (BOM) count, and enables ease-of-use while shortening the time to market. This paper reports the latest improvements achieved on a GaN IPS based 65W charger/adapter application demonstrator.

Design and Performance Analysis of High Density Universal Charger featuring GaN based Integrated Power Stage

A three-level gate driver and a power GaN HEMT were integrated on a monolithic chip by an Enhancement-mode GaN-on-SOI process. The chip realises high speed switching and effective three-level gate driving without any external negative power supply. However it has a problem of low heat dissipaton in continuous operations because of the BOX layer and the deep trenches for isolating power devices. Then, the IC was implemented in a C-QFN package and evaluated the tolerance for continuous operation with measuring the case temperature. The measurement result shows that the GaN IC can safely operate continuously in condition of the storage temperature below 64◦C. We attempted to design a small and high power density converter using the fabrication chip.

An Asynchronous Buck Converter by Using a Monolithic GaN IC Integrated by an Enhancement-Mode GaN-on-SOI Process

As the DC current has no natural zero crossing, the development of the DC breakers are much more challenging compared to the AC breakers. In this paper, a Gallium Nitride (GaN) switch-based Resonance Current Source (RCS) is modeled, designed, built, and tested. The RCS was tested separately and in a hybrid dc breaker system for creating an artificial zero current crossing in a vacuum interrupter of a medium voltage Ultra-fast Resonance Direct Current Breaker (UFRDCB). Finally, the performance of the RCS is verified by experiment and the results are presented.

Modeling, Simulation and Hardware Implementation of the GaN Based Resonance Current Source for the Ultra-Fast MVDC Circuit Breaker

Gallium nitride high-electron mobility transistors (GaN HEMTs) have superior switching performance, when compared to similarly rated silicon switches. High switching frequency operation is enabled by low switching transition times
and switching losses. High switching frequency can be beneficial in an electric drive, as the output filter size can be decreased, and furthermore a sinusoidal inverter output current produces low motor losses and torque ripple. Nevertheless, the performance of GaN HEMTs in high switching frequency three-phase inverters
remains unraveled. In this paper, the design and implementation of a three-level ANPC inverter prototype employing GaN HEMTs and a 1 MHz switching frequency is presented. The measured output voltage and current waveforms are sinusoidal, however, some distortions are visible due to modulator design. Furthermore,
the prototype exhibits a peak efficiency of 96.56% at 2.1 kW output power with an LR load.

Three-phase three-level GaN-ANPC inverter with a 1 MHz switching frequency

We investigate the influence of trap filling conditions on the extraction of the emission time constant (τ) of deep levels associated with Fe doping in AlGaN/GaN HEMTs. To this end, we monitor the drain current transients (DCTs) after a short (1 µs) trap filling pulse and investigate the effect of varying (i) gate voltage (VGS,fill) and (ii) drain voltage (VDS,fill) applied during the filling pulse. We find that the extracted τ weakly depends on VGS,fill and it decreases for VDS,fill below 40 V; instead, for VDS,fill > 40 V τ saturates to a value corresponding to the inverse of the emission rate (1/en) at room temperature. The decrease of τ with decreasing VDS,fill was explained with the aid of numerical simulations, by attributing it to the concurrent effect of both emission and capture processes during DCT. This dependence must be taken into account when using DCT to characterize trap emission dynamics in order to correctly estimate the capture cross-section from Arrhenius plots.

Effect of Trap-Filling Bias on the Extraction of the Time Constant of Drain Current Transients in AlGaN/GaN HEMTs

Low temperature power electronics is beneficialin many different applications. Wide band gap (WBG) devices are becoming increasingly popular due to their high performances over the traditional silicon (Si) technology. Different from the gallium nitride (GaN) enhancement mode (E-mode) device, the cascode GaN is composed of a low voltage Si MOSFET and a depletion mode GaN. The advantages of the cascode GaN over E-mode GaN are: 1) easy of drive; 2) high noise immunity. In this article, the cryogenic evaluation results, including both static and dynamic characterizations, for a state-of-the-art high performance 650 V GaNcascode field-effect transistor (FET) are presented and analyzed. The evaluated 650 V cascode GaN FET has better performance under cryogenic temperatures, like low on-state resistance, large threshold volatge, reduced switching times and switching losses. Comparison resultswith the 650 V E-mode GaN device are made, the results demonstrate that the cascode GaN would be more reliable due to the high threshold voltage.

Evaluation of the High Performance 650 V Cascode GaN FET under Low Temperature

Abstract— In this work, the humidity performance of three enhancement mode GaN HEMTs with different chip designs and packages from different manufacturers were investigated by a High Humidity, High Temperature, Reverse Bias (H³TRB) test. The devices were tested until end of life (EoL) with a few devices even surviving the end of the test after passing 6000 test hours. Some of the devices provided a precursor of the catastrophic failure, while others just failed suddenly. There were little changes in the characteristics obtained at intermediate measurements. The Weibull analysis of the failures shows a consistent and clear wear-out behaviour. These results document an excellent humidity capability of the tested GaN devices even outperforming usual silicon devices, although GaN devices exhibit smaller insulation distances and higher electric fields. However, during the initial phase of the test conductive anodic filaments (CAF) formed in the PCB adapters and compromised the leakage current readings such that the adapters had to be removed to be able to continue the test. In other words, the weakest spot is no longer the semiconductor device itself, but has moved to other components in the circuitry.

Humidity Capability of Enhancement Mode GaN High Electron Mobility Transistors

This paper provides the extra loss caused by
dynamic ON-Resistance in a soft-switching converter seeking to
incorporate it into the design process, studying its dependence on
temperature and switching frequency. Firstly, characterization
is conducted in double-pulse tests to verify some impact factors
which may vary in converter operation. Different operation
modes, hard-switching, soft-switching, and reverse conduction at
various temperatures, can be achieved using the full-bridge
schematics with an extra resistor. Secondly, a series resonant
converter is built based on the same testbed and an additional 16.8% conduction loss was observed in the worst case.

Dynamic ON-Resistance Characterization of GaN HEMT Under Soft-Switching Condition

Transphorm Inc. is supplying N-polar GaN epitaxial wafers for ultra-high-performance RF and mm-wave electronics on sapphire and silicon carbide (SiC) substrates. In this work, we report on the manufacturing facility, epitaxial growth on
both 100-mm sapphire and 100-mm SiC, and device electrical performance. Results show good material quality, a low 2DEG sheet resistance with good uniformity, and good dynamic behavior with no current dispersion at 60 V at both room temperature and high temperature (150°C).

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Next from IEEE WiPDA 2021

Modulation Strategy Comprising TCM with Frequency Limit and DPWM for Fast Switching GaN-Inverters

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