United States

This paper presents a comparison between the operation of a 13.56 MHz Class Phi2 inverter using one or multiple gallium nitride (GaN) switching devices in parallel. In high-frequency, high-power applications such as plasma generation, the GaN device is advantageous due to its low switching losses and on-resistance, evident in 
simulations. However, as the frequency and power increase, the power dissipation in the devices increases. Using device parallelization for current splitting, we can reduce the losses, which leads to lower device heating, thereby reducing device stress and enhancing the overall thermal management. This paper shows that current splitting effectively reduces the temperature rise across an individual switching device. Using the optimal number of paralleled devices, the steady-state case temperature of each device is almost halved in a multi-device inverter compared to a single-device inverter.

IEEE WiPDA 2021

Paralleling Devices in a 13.56 MHz Class Φ2 Inverter to Achieve Current Splitting and Improve Device Thermal Performance

After two years of virtual conferences, we're excited to host EMC 2022 in person at The Ohio State University in Columbus, Ohio. In addition to cutting-edge technical presentations given in multiple parallel sessions, opportunities to network with colleagues will be present throughout the conference. The size and format of the meeting makes networking easy, whether you have been coming to the conference for many years or are a first-time attendee.

EMC is coordinated with the Device Research Conference (DRC), which will be held the same week, from June 26-29. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

For information on the 80th Device Research Conference, please visit the DRC 2022 website.



EMC 2022

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

technical paper

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

**Topics of interest**

* Heteroepitaxial & Bulk Materials Growth
* Gate Dielectrics & Surface Passivation
* Device Structures & Fabrication Techniques
* Device Characterization & Modeling
* Very-High Efficiency or Compact Converters
* Safe Operating Areas of Wide Bandgap Devices, Including Short Circuit, Spike, & Transient Tolerance
* Harsh Environment (High Temperature) Operation & Reliability
* Packaging Power Modules & ICs
* Hard-Switched & Soft-Switched Application Analysis
* Gate Drive & Other Auxiliary Circuits
* High-Performance Passive Components
* Applications in Renewable Energy & Energy Storage, Transportation, Industrial Drives, & Grid Power Systems
* Wide Band Gap System Design Philosophies & Strategies
* Radio Frequency (RF) GaN (New)
* Technology Roadmap of Wide Bandgap Including Devices, Applications and Packaging (New)

### Please select the button below to view and download the session papers. The Virtual Proceedings PDF can be downloaded [here.](https://drive.google.com/file/d/171y2_u63V-pc9-bC-eZgHLzJou2oCfST/view?usp=sharing)

[![](https://assets.underline.io/uploads/markdown_image/1/image/c8e1b0a2881d3bb0a75ece4761f43c9f.png)](https://drive.google.com/drive/folders/1GWEFLzH6K4aUBaJiBFJDw4x9sKLTl6-g?usp=sharing)


This event requires a registration to attend, please register [here](https://web.cvent.com/event/536cea3d-4c0d-4d50-8939-529979d80785/summary) to purchase a ticket. 

The IEEE Workshop on Wide Bandgap Power Devices & Applications (WiPDA) provides a forum for device scientists, circuit designers, & application engineers from the Power Electronics & Electron Devices Societies to share technology updates, research findings, experience & potential applications.

In this work, 15 kV 4H-SiC Split-Gate Vertical Planar MOSFETs (SG-MOSFET) are demonstrated for the first time. Both the traditional MOSFET and SG-MOSFET were fabricated on the same 6-inch SiC wafer and achieved maximum breakdown voltages (BV) of 15930 V and 15080 V, respectively. This is the first demonstration of the split gate architecture on SiC for voltage ratings above 10 kV, and this BV was achieved using a Hybrid-Junction Termination Extension (JTE) edge termination. The fabricated SG-MOSFETs showed a reduction in gate charge as well as no significant deviation in forward conduction and blocking behavior when compared to their MOSFET counterparts. These results display the SG-MOSFET’s potential for lower switching power losses in ultra-high voltage devices without compromising device static performance. In the following text, the layout, static performance, and gate charge of the MOSFET and SG-MOSFET are described to show the exciting potential of the high voltage SG-MOSFET.

Demonstration of High Voltage (15kV) Split-Gate 4H-SiC MOSFETs

Several designs of 1.2kV-rated 4H-SiC JBS diode integrated MOSFETs (JBSFETs) have been successfully fabricated in order to increase the 3rd quadrant device performance while having negligible effect on both the forward and blocking modes of operation. Incorporating the Schottky area in an efficient manner to improve overall device performance has been one of the critical paths in the development of 4H-SiC JBSFETs. Device design, fabrication, and electrical performances are discussed in this presentation.

Increased 3rd Quadrant Current Handling Capability of 1.2kV 4H-SiC JBS Diode-Integrated MOSFETs (JBSFETs) with Minimal Impact on the Forward Conduction and Blocking Performances

SuperCascode Power Switches (SCPS) use series-connected Low Voltage (LV) - High Current (HC) devices in a serial string to realize High Voltage (HV) – HC power switches. Cascading of SuperCascodes (CSC) is a modification of the earlier proposed SCPS concept aimed to scale the switching topology to very high (>100 kV) levels or applied to optimize previously reported HV SCPSs to achieve higher switching speed, reduced balancing network size and lower switching losses. However, certain practical challenges create engineering constraints in design which will be discussed and highlighted in this paper. Firstly, for a serial string of devices, scaling the devices adds stray inductances which lead to delays in triggering serial devices, de-synchronization of triggering and unexpected overvoltages that limit scalability. This paper provides an analytical model to enable optimization through simulation and provides experimental data verifying the model.

Analytical Method to Optimize the Cascaded SuperCascode Power Switch Balancing Network

Bidirectional, or four-quadrant switches (FQS) can be designed as back-to-back MOSFETs connected in common-drain (CD) or common-source (CS) topologies. CD-FQS and CS-FQS assembled from discrete 1.2 kV commercially available SiC Power MOSFETs were characterized to obtain capacitance and switching loss values. The CD-FQS exhibited a 1.6x larger turn-off loss compared to the CD-FQS. The CS-FQS exhibited a lower input capacitance, while the CD-FQS exhibited a lower output and reverse transfer capacitance.

Comparison of the Capacitances and Switching Losses of 1.2 kV Common-Source and Common-Drain Bidirectional Switch Topologies

This paper reports the design and process flow of a fully integrated yet isolated low-voltage (LV) CMOS with high voltage (HV) lateral power MOSFET on a 6-inch 4H-SiC substrate for the development of HV SiC power ICs. The epi stack (N-epi/P-epi on N+ substrate) for the development of the power ICs was optimized to accommodate and isolate the HV devices and circuits from their LV counterparts. The devices reported in this work were fabricated at 150mm, production grade-Analog Devices Inc. (ADI) Hillview fabrication facility located in San Jose, CA. The HV lateral NMOSFET from this work demonstrated a breakdown voltage (BV) of 620V and a specific on-resistance (Ron,sp) of 9.73 mΩ⸱cm2 at gate-source voltage (Vgs) of 25V. A single gate oxide and ohmic process were used to fabricate the HV NMOS and LV CMOS devices and circuits. Junction isolation was implemented for isolating the HV and the LV blocks for the design of HV Power ICs. Finally, this work executed an HV capable three-metal layered back-end-of-the-line (BEOL) process, an imperative provision for developing reliable and robust power ICs. For future high-temperature applications, the static performances of the devices are characterized and are reported up to 200oC.

Development of Isolated CMOS and HV MOSFET on an N-epi/P-epi/4H-SiC N+ Substrate for Power IC Applications

In this paper, a direct bonded GaN intelligent power module (IPM) with liquid cooling is demonstrated. A half bridge module with GaN high electron mobility transistors (HEMTs) is bonded on active metal brazed (AMB) substrates which are pre-brazed on a copper liquid-cooled heat exchanger. The design of this power module, such as the selections of the GaN dies and the placement of the GaN dies with respect to the AMB dimensions, is determined based on thermal simulations, estimated electrical parasitics and experiments. The prototype GaN IPMs are demonstrated in a buck converter configuration. The modules are tested up to 110 W with top surface temperature of the PCB module kept below 125 °C, measured by an infrared camera (FLIR). The proposed IPM with liquid cooling offers an effective packaging solution for electric vehicle applications.

Compact GaN Power Modules with Direct Bonded Liquid-Cooled Heat Exchanger Suitable for EV Applications

This paper presents an approach to measure the online junction temperature of wide bandgap (SiC and GaN) power transistors using quasi turn-on delay as a temperature-sensitive electrical parameter with the possibility of adjustable temperature sensitivity. A double pulse test setup is implemented for both of the power devices and a time-to-digital converter is used for the quasi turn-on delay measurement which requires two timestamps to measure the intermediate time. The switching signal from the function generator is used as the first trigger to start the timer and for the second trigger to stop the timer, the voltage drop across the parasitic inductor between the Kelvin and power source is used. The novelty of the proposed method is to measure quasi turn-on delay independent of other electrical parameters such as DC-link voltage.

Online Junction Temperature Monitoring of Wide Bandgap Power Transistors using Quasi Turn-on Delay as TSEP

Exposure to an extreme ambient temperature leads
to increased losses in a Gallium Nitride Field Effect Transistor
(GaN-FET) when operating in a switch-mode power stage. The
output capacitance of Gallium Nitride (GaN) devices is decreased
at higher voltages but increased at higher temperatures. This
paper highlights the effect of output capacitance in a halfbridge switching stage and offers analysis towards the switching
losses. A power stage was build and tested with two timing
optimizations for room temperature and high temperatures,
respectively. Trading off dead time and the loss mechanisms
involved, a loss reduction of 16.1% was achieved. A loss reduction
was further improved to 26.1% after, thorough investigation of
the switch node transient responses.

Switching Performance in a GaN Power Stage at Extreme Temperature Conditions

The power electronics industry is adopting Gallium Nitride (GaN) devices for use in switching power converters, and engineers need to understand how GaN HEMTs perform in-circuit. Given that dynamic resistance varies with operating conditions, in-circuit characterization provides an invaluable measurement tool. Aerospace has developed a method that works independently of the power stage topology, using inexpensive and widely available measurement hardware. Instead of the traditional clamp, the circuit actively controls the open-loop power-stage and directly senses the on-state voltage. This approach enables measurement in the application’s power stage, which includes the true current-voltage loci and parasitic elements, providing more insight than pulsed IV or double pulse measurements.

A Generalized Circuit for Measuring GaN Dynamic Resistance

DC and battery-powered motor applications are shifting from conventional silicon MOSFET-based, low PWM frequency inverters to GaN-based, high-frequency PWM
inverters. The advantages lie in the higher system efficiency and in the elimination of the electrolytic capacitors, and the DC input filter. In this paper, gallium nitride-based devices are shown to increase power density to a new level and move to high-frequency PWM inverters with negligible dead time for electric motors used
in many different applications including, but not limited to servo drives, e-bikes, e-scooters, collaborative and low-voltage robot, medical robots, industrial drones, and service-motors used in automobiles.

Premium content

Downloads

Next from IEEE WiPDA 2021

Demonstration of High Voltage (15kV) Split-Gate 4H-SiC MOSFETs

Similar lecture

Phase Composition and Microstructure of κ-Ga2O3 Heteroepitaxial Films Grown by MOCVD