Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9168.pdf

**Abstract:**

This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) &amp; 1.0pJ/b (PAM8).

ESSCIRC ESSDERC 2021

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET

serdes

pam4

transmitter

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9168.pdf

**Abstract:**

This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).

technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9145614

**Abstract:**

This paper presents a widely tunable digital delay element suitable for low-power low-frequency continuous-time digital signal processing systems. The design uses features of the 28 nm FD-SOI CMOS technology to precisely control currents in the pA range and significantly reduce leakage power. The measured tuning range is significantly larger than prior art covering more than 3 decades from 30 ns to 100 µs making it suitable for CT-DSP low frequency filters. At 0.7 V supply voltage, the dynamic power consumption is 15 fJ/event with a residual power consumption due to leakage of 14 pW.

A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9033.pdf

**Abstract:**

Accurate split-CV mobility measurements require to overcome Bias Temperature Instabilities (BTI) which are a key issue in GaN-on-Si MOS-channel HEMTs. In this article, a rigorous methodology to extract the split-CV mobility as a function of the electron density and the temperature at Al2O3/GaN interface is depicted. Drain current ID(VG) and gate-to-channel capacitance CGC(VG) measurements are performed simultaneously under fast gate voltage ramp to prevent BTI. The voltage ramp enables fast CGC(VG) measurements and allows to bypass the frequency effect which can be observed when using small signal capacitance measurements. Thus, this technique paves the way to a reliable determination of intrinsic electron transport properties of GaN transistors.

Reliable Method for Low Field Temperature Dependent Mobility Extraction at Al2O3/GaN Interface

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9121.pdf

**Abstract:**

Gate-to-channel coupling capacitance behavior on GaN-HEMT with recessed MIS-Gate was analyzed combining experimental data and 2D-simulations. A new protocol to discriminate the contribution of the active channel and of the different coupling parasitic capacitances on a C-V curve of a GaN MIS-HEMT is proposed. It also enables the evaluation of the respective contributions of all parasitic components such as passivation layer and gate field plate capacitances in the parasitic capacitance of GaN HEMT devices.

Parasitic Capacitance Analysis in Short Channel GaN MIS-HEMTs

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9039.pdf

**Abstract:**

The reduction of substrate RF losses and non-linearities is key to enable high-performance GaN-on-Si HEMT based RF front-end modules. In this paper, the impact of the epitaxial III-N buffer layers on substrate RF losses and harmonic distortion is studied experimentally using coplanar waveguide (CPW) structures. In contrast to a SiO2/Si stack, a strong hysteresis in the RF losses (quantified using effective resistivity) of the HEMT stack is observed when the chuck DC bias is swept. A comparative analysis of various material stacks suggests that the hysteresis originates from the large time constants (much larger than 1 s) associated with the traps in the III-N layers. Harmonic distortion, on the other hand, shows much weaker hysteresis effect than effective resistivity during chuck bias sweeps.

Impact of III-N Buffer Layers on RF Losses and Harmonic Distortion of GaN-on-Si Substrates

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9145.pdf

**Abstract:**

Low-temperature, low-resistive and gold-free Ta/Al-based ohmic contacts fabricated by sputtering on AlGaN/GaN-heterostructures are demonstrated on 150mm GaN-on-Si substrates using Ta/Al/TaN stacks annealed at 550°C, being suitable for integration of GaN-based devices in Si-platforms. The low-temperature annealing improves the sheet resistance thermal stability of heterostructures without passivation. Moreover, the weaker increase with temperature of the contact resistance given by the 2DEG-semiconductor-metal connection governed by tunneling for Au-free Ta/Al-based contacts, rather than the stronger temperature increase of the contact resistance given by the direct metal-2DEG connection for Au-containing Ti/Al-based contacts, results beneficial for HEMTs operating at high-temperature by reducing the on-resistance degradation.

Integration and Reliability Aspects of Low-Temperature and Au-Free Ta/Al-Based Ohmic Contacts for AlGaN/GaN MIS-HEMTs

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9173.pdf

**Abstract:**

This paper demonstrates a compact BLE transmitter (TX) achieving fully on-chip integration and high system-efficiency. This BLE TX is constructed based on a 1.2 GHz 8phases current-reused ring oscillator (RO) with a digital phase-locked loop (PLL). To mitigate the spurious emission, including HD2 caused by phase mismatches, an edge-timing calibration is proposed by reusing the digital PLL in this paper. A transformer-based Class-D PA with implicit LC-notch is implemented to improve the system efficiency with higher harmonic suppression for both HD2 and HD3 with a compact on-chip area. The presented TX supports both 1 Mbps and 2 Mbps GFSK modulation with low power consumption.

A 0.25mm² BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9187.pdf

**Abstract:**

A low power multi-mode transceiver IC is presented to support 802.11b/g/n/ax, Bluetooth classic (BT) and low energy (BLE). The design features two signal paths and one merged RF port, demonstrating the first combo chip optimized for low power IoT applications. With the proposed power saving architecture, the combo chip presents comparable or better performance against standalone solutions. The receiver chain noise figure (NF) is measured at 2.7dB in 802.11ax mode, and the power consumption is 32mW, the lowest reported in its class. In BLE receiving mode, NF is 5dB while consuming 9.7mW. The measured 802.11 mask compliant output power is 21.5dBm with 22%/20% PA/Tx efficiency. With 1024-QAM OFDM (MCS11) signals, -35dB EVM is achieved at 16dBm output power without digital pre-distortion (DPD). EVM floor reaches -42dB with 11n MCS7 signals. As for BLE transmission, 10.5dBm power can be delivered with 28%/21% PA/Tx efficiency. Implemented in 22nm CMOS technology, the entire radio occupies 2.1mm^2 silicon area.

A Highly Efficient Combo Transceiver for 802.11b/g/n/ax and BT/BLE in 22nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9161.pdf

**Abstract:**

This paper presents a transmitter concept which generates a wide coherent modulation bandwidth. The proposed FDDAC based Tx concept exploits the relation between the discrete and continuous-time Fourier Transform leading to intrinsic Nyquist filtering. Thus, the sampling rates in the analogue-mixed-signal and the DSP domains are reduced by up to two orders of magnitude compared to conventional Txs. The experimentally verified integrated Tx-IC for 802.11ad/y applications generates a single-carrier 16QAM signal with a modulation BW of up to 2GHz. The measured EVM values are 7.2% and 11.8% for a 1 and 2GHz QPSK signal, respectively, whereas they are 9.6% and 13.9% for a 1 and 2GHz-wide 16QAM signal.

FDDAC-Based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9113.pdf

**Abstract:**

Noise-shaping is essential for Direct Digital to RF (DDRF) transmission but filtering of Out of Band (OOB) quantization noise is difficult at 6 GHz for Wi-Fi 6E. We present a filter-free DDRF architecture that introduces targeted noise-shaping (TaNS) to meet the spectral mask. TaNS attenuates quantization noise at offsets between one and ten times the bandwidth by moving it far out-of-band. The prototype is fabricated in 28nm CMOS with an active area of 0.022 mm2 and shows the feasibility of 64-QAM modulation up to 281 Mbps.

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9157.pdf

**Abstract:**

As wireline transceivers continue to push for higher speeds, their power consumption becomes increasingly more critical. This paper describes methods that can reduce the power drawn by drivers and multiplexers on the transmit side and equalizers and clock and data recovery circuits on the receive side. These concepts have been incorporated in designs ranging from 40 Gb/s to 80 Gb/s in 45-nm and 28-nm process nodes.

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