Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9145614

**Abstract:**

This paper presents a widely tunable digital delay element suitable for low-power low-frequency continuous-time digital signal processing systems. The design uses features of the 28 nm FD-SOI CMOS technology to precisely control currents in the pA range and significantly reduce leakage power. The measured tuning range is significantly larger than prior art covering more than 3 decades from 30 ns to 100 µs making it suitable for CT-DSP low frequency filters. At 0.7 V supply voltage, the dynamic power consumption is 15 fJ/event with a residual power consumption due to leakage of 14 pW.

ESSCIRC ESSDERC 2021

A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS

ultra low-power circuits.

fully depleted silicon-on-insulator (fd-soi) cmos

event-driven systems

digital delay

continuous-time digital signal processing (ct-dsp)

sensors

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9116.pdf

**Abstract:**

A 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close-by large reflectors and the system power consumption is 67mW.

A 67mW D-Band FMCW I/Q Radar Receiver with an N-Path Spillover Notch Filter in 28nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9059.pdf

**Abstract:**

This paper presents a transmitter(TX) and an adaptive receiver(RX) for the next-generation automotive camera link with PAM-4 signaling. TX utilizes push-pull current drivers and 3-tap FFE to improve impedance matching and eye margin, respectively. To cancel the sampler offset for a lower BER, instead of adjusting data and threshold levels(dtLevs), the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The TX delivers 8-Gb/s PAM-4 signal to the adaptive RX through a 12-m cable(22-dB loss) with a BER of 1E-8. The prototype chips consume 65.2 mW(excluding PLL), exhibiting an FoM of 0.37 pJ/bit/dB.

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9062.pdf

**Abstract:**

This work presents a dielectric waveguide communication link at 135 GHz, reaching 27 Gb/s non-return to-zero (NRZ) communication without any equalization at a bit-error-rate (BER) below 10-12 and up to 50 Gb/s 4-level pulse-amplitude modulation (PAM4) over 3 m of fiber at a BER below 10-6 when equalization is applied. This work is the first to break the 25 Gb/s barrier at distances of 1 m and above. These results are achieved by combining a low power, multilevel mm-wave transceiver with a coupler on printed circuit board (PCB) and a fiber design optimized for low dispersion.

A PAM4 Dielectric Waveguide Link in 28 nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9253.pdf

**Abstract:**

A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 25.3 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25%duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.

200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9172.pdf

**Abstract:**

This paper presents a real-time output 50-GS/s 8-bit time-interleaved (TI) analog-to-digital converter (ADC) with dedicated calibration techniques and deterministic latency, where the full-speed converted data are output by 16-lanes transmitters. gain, offset and time-skew calibration optimize the ADC\'s performance. Fabricated in a 40-nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.80 dB at 50 GS/s with a 19.123-GHz input. respectively. The ADC core occupies an area of 1.232 mm2 and consumes 894 mW.

A Real-Time Output 50-GS/s 8-Bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9115.pdf

**Abstract:**

This paper presents a 6GS/s 0.5GHz bandwidth CT 2-1-1 MASH 3b ΔΣ modulator in 40nm CMOS. To enable the 0.5GHz bandwidth, the modulator employs current-mode excess loop delay compensation with phase boosting, current-mode locally-time-interleaved quantizers, and on-chip comparator offset calibration to realize high-speed ELD-compensated 3-bit quantizers. High sampling frequency, multi-bit quantization and multi-stage noise-shaping enable the ADC to achieve 58dB DR in 500MHz BW when sampled at 6GHz. If sampled at 4GHz, 65dB DR can be achieved at a BW of 300MHz.

A 6GS/s 0.5GHz BW Continuous-Time 2-1-1 MASH ΔΣ Modulator with Phase-Boosted Current-Mode ELD Compensation in 40nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9308.pdf

**Abstract:**

This paper reports the first silicon-verified current-steering DAC using enhanced constant-switching-activity data-weighted-averaging (CSA-DWA). It achieves data-independent constant switching activities for all the input codes by exploiting redundant switching elements. In addition, a power supply network optimization is presented to meet the increased timing-match requirement due to the adopted extra switching elements. Without calibration, the fabricated 16-bit 4GS/s DAC in 65nm CMOS achieves >70dBc spurious-free dynamic range (SFDR) and <-80dBc third-order intermodulation distortion (IM3) up to 1GHz, showing 4-15dB SFDR and 5-14dB IM3 improvement across the Nyquist band.

A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 Up to 1GHz Using Constant-Activity Element Switching

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199821

**Abstract:**

A triple-mode RF system on a chip (SoC) is reported which supports cellular Internet of Things (IoT) standards eMTC, NB-IoT, and EC-GSM, as well as 2G fallback. In the eMTC mode, the SoC achieves best-in-class performance for reference sensitivity (-112.3 dBm), coverage extension mode A (-128.5 dBm) and B (-136.8 dBm), respectively. A very efficient RTC, combined with dynamic power management of unused clocks and idle blocks, also leads to excellent performance in cellular IoT power-saving modes, such as extended discontinuous reception and power-saving mode.

A Triple-Mode Cellular IoT SoC Achieving −136.8-dBm eMTC Sensitivity

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9145702

**Abstract:**

This work presents a true random number generator (TRNG) based on a stochastic delta-sigma modulator (DSM) with ring oscillator (RO) integrators. The TRNG leverages noise and jitter in the ROs as an entropy source. A multi-bit non-return to- zero (NRZ) digital-to-analog converter (DAC) in the feedback path ensures DSM noise dominates input swing seen by the frontend integrators. Hence, the DSM can concurrently operate as an ADC and TRNG. A 65nm prototype achieves Shannon entropy > 0.999998 with lower-bound min-entropy > 0.995 at 52Mbps throughput while passing all NIST tests across multiple chips and voltage/temperature corners without needing calibration. The combined power consumption of ADC and TRNG is 0.36mW which is the lowest among state-of-the-art RO TRNGs. Low power consumption, high entropy, and concurrent operation of the TRNG as an ADC are principal contributions of this work.

0.36mW, 52Mbps True Random Number Generator Based on a Stochastic Delta-Sigma Modulator

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9195478

**Abstract:**

An all-digital flexible precision in-memory accelerator for vector matrix multiplication (VMM) is demonstrated in 65 nm CMOS. The design supports flexible precision, floating point, and complex numbers enabling in-memory radio-frequency machine learning and signal processing computation. The measured compute efficiency normalized to memory size is 34 GOPS/W/KB.

A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS

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