Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9019.pdf

**Abstract:**

This paper presents a rail-to-rail class-AB operation amplifier with a proposed high-slew Miller compensation technique and current limiter for the output stage. Owing to the proposed Miller compensation technique, the amplifier achieves a maximum slew-rate of 30 V/μs while consuming a low quiescent current of 18μA. Among the state-of-the-art devices, the proposed amplifier has the best FOML of 34.72 for average slew-rate and FOMS of 10.11 for unity gain frequency.

ESSCIRC ESSDERC 2021

A 18 μA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 μm

current limiter

miller compensation

high-slew

negative feedback

amplifier

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9265.pdf

**Abstract:**

This paper presents a new method to reliably simulate the PDE and jitter for realistic 3D device simulations of SPAD devices. This method is based on the use of electric field lines to mimic the carriers\' trajectories, which allows the transformation of a 3D problem into a multitude of 1D problems. This idea is applied to the McIntyre model for breakdown avalanche probability to calculate PDE, but also for jitter prediction using a dedicated advection-diffusion model. The results obtained numerically are compared with an extensive series of measurements and show a good agreement on a wide variety of device designs.

Comprehensive Modeling and Characterization of Photon Detection Efficiency and Jitter in Advanced SPAD Devices

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9213.pdf

**Abstract:**

In this work, a wafer-scale fabrication of biologically sensitive Si nanowire FET is demonstrated for pH sensing and electrical detection of DNA hybridization. Based on conventional “top-down” CMOS compatible technology, our bioFETs explore a wide range of design (nanowires (NW), nanoribbons (NR), and honeycomb (HC) structures) with opening access scaled down to only 120 nm. After device fabrication, IDS-VBG transfer and IDS-VDS output characteristics show a conventional n-type FET behavior with an ION/IOFF value higher than 105, as well as an increase of threshold voltage (VTH) as the NW width is reduced. Then, using a capacitive coupling in our dual-gated Si bioFETs, the pH sensitivity is enhanced with a pH response up to 600 mV/pH. Finally, the increase of threshold voltage of n-type SiNWs due to the hybridized target DNA molecules is successfully detected

Wafer-Scale Fabrication of Biologically Sensitive Si Nanowire FET: From pH Sensing to Electrical Detection of DNA Hybridization

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9258.pdf

**Abstract:**

A CMOS industry compatible integrated resonant SiN gyroscope was fabricated with the STMicroelectronics 300 mm Photonic R&D platform. For the first time, both active Si&Ge components and low loss SiN resonant ring are integrated in an optical gyroscope, based on a ring resonator coupled to a Mach-Zehnder Interferometer. Modeling of the shot noise resolution of our device is given, resulting in a resolution of 1.08deg/s. Experimental measurement show a static gain in sensitivity of 56% compared to a single ring with the same footprint.

Design and Fabrication of a Ring-Coupled Mach-Zehnder Interferometer Gyroscope

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9287.pdf

**Abstract:**

In this work we propose and experimentally validate a relaxation oscillator architecture with ultra-high tuning range (higher than 400%, from 5KHz to more than 25kHz when the control voltage is varied from 2.5 to 5V) that exploits the reversible metal-insulator transition in 2-terminal Vanadium Dioxide thin film devices loaded to a MOSFET common source amplifier. We propose and validate an analytical model that connects key output signal metrics to the intrinsic properties of the phase-change VO2 device employed. In addition, we demonstrate RF and optical sensing capabilities, with sensitivities of 4.64 Hz/dBm and 4.23 Hz/mW to RF and Optical Power, respectively.

High Tuning Range Spiking 1R-1T VO2 Voltage-Controlled Oscillator for Integrated RF and Optical Sensing

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9158.pdf

**Abstract:**

This paper benchmark the intrinsic trade-off between two essential modules of gate-all-around GAA nanosheet (NS)FETs viz. inner-spacers (ISPs) epi-induced stress in the channel. While having both ISPs and the stress is the best-case scenario for NSFET, it comes with enhanced process challenges and performance risks: poor epi-quality resulting in a no-channel stress scenario. While inner-spacers are important to parasitic capacitance reduction, we show that having intrinsic epi-stress is more beneficial and provides a better performance trade-off. We further evaluate the impact of inner-spacer κ-value and enhanced epi-volume for the two different cases. Finally, we have performed self-heating studies to show how skipping inner spacers can provide additional reduction in peak temperature.

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-Spacers and Epi-Induced Stress: Understanding & Mitigating Process Risks

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9202.pdf

**Abstract:**

We explore charge and spin transport properties of bilayer CrI3 controlled by an external electric field. To this aim, we focus on two different device structures, namely Monolayer/Bilayer/Monolayer CrI3 and Bilayer/Bilayer/Bilayer CrI3. The electric field is only applied to the central Bilayer-channel. In the first device, we inject only a single spin from the ferromagnetic Monolayer CrI3 which allows us to study its effect on the spin transport properties of a spin transistor. The second structure is based on the injection of both spins, that are later filtered, resulting in spin-filter device.

Electric-Field Controlled Spin Transport in Bilayer CrI3

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9141.pdf

**Abstract:**

We present a circuit model for the co-simulation of spin qubits with their control and readout electronics in a common simulation environment. The model, completely simulated in Spectre, can handle all the basic operations on spin qubits, including readout and universal single and 2-qubit quantum gates. Furthermore, the model has the ability to include nonidealities such as decoherence and noisy control signals, thereby paving the way for circuit-technology co-optimization for spin-based quantum computation.

Circuit Model for the Efficient Co-Simulation of Spin Qubits and Their Control & Readout Circuitry

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9106.pdf

**Abstract:**

In this work, we report the characterization and modeling of a 14 nm bulk FinFET technology from room-temperature down to 4.6 K. A cryogenic device model is used which shows excellent fit to measured data and can accurately predict the performance of the devices at low temperatures. The obtained results show that a tailored cryogenic FinFET technology could achieve a sharp reduction of dissipated power by reducing the drive bias. Such technology has potential for strong impact e.g. in quantum computing, by enabling integration of dense advanced cryogenic ICs inside the cryostat.

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9137.pdf

**Abstract:**

This study presents the first in depth characterization of deep cryogenic electrical behavior of a commercial 16nm CMOS FinFET technology. This technology is well suited for a broad range of applications, including quantum computing, quantum sensing, and quantum communications. Cryogenic DC measurements and physical parameters extraction were carried out on this commercial FinFET technology, operating at room temperature, i.e., 300 K, and down to 2.95K for different device types and geometries. This represents the main step towards cryogenic compact modeling and optimization of three-dimensional CMOS structures for quantum computations.

Cryogenic Characterization of 16 nm FinFET Technology for Quantum Computing

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9104.pdf

**Abstract:**

This paper reports a chopper Class-D audio amplifier that obtains high PSRR over the entire audio band. A chopping scheme is proposed to minimize intermodulation distortion between pulse-width modulation (PWM) and chopping in the audio band. A high-voltage chopper is developed to handle a 14.4 V PWM signal. Timing matching techniques are proposed to minimize chopping nonidealities which ensure good PSRR and THD. Fabricated in a 180nm BCD process, the prototype obtains a PSRR >109 dB at 217 Hz and >83.7 dB over the entire audio band. It also achieves −109.1 dB/−98 dB THD/THD+N and can deliver a maximum of 13 W to an 8-Ω load.

A 18 μA Rail-to-Rail Class-AB Operational Amplifier with a High-Slew Miller Compensation (HSMC) Technique with 240% Settling Time Reduction in 0.18 μm

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