Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9197.pdf

**Abstract:**

We here report a joint experimental and theoretical analysis of polarization switching in ferroelectric tunnel junctions. Our results show that the injection and trapping of charge into the ferroelectricdielectric stack has a large influence on the polarization switching. Our results are relevant to the physical understanding and to the design of the devices, and for both memory and memristor applications.

ESSCIRC ESSDERC 2021

Polarization Switching and Interface Charges in BEOL Compatible Ferroelectric Tunnel Junctions

synaptic devices

ferroelectricity

neuromorphic computing


![](https://assets.underline.io/uploads/markdown_image/1/image/2e10c515564e9ec3287ee4c664011c20.png)

The energy cost of storing and moving data is enormous, and is growing at such a rapid pace that within a few years the power demand may overwhelm some developed nations. Non-volatile memory (NVM) and neuromorphic computing are enabling critical advances in this area, but there are many scientific and technological challenges. This conference will cover the materials challenges of different memory technologies, from the fundamental processes and mechanisms, to industry perspectives on materials specifications and manufacturing.

Materials Challenges for Memory

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199382

**Abstract:**

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-allaround stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

Ultrahigh-Density 3-D Vertical RRAM with Stacked Junctionless Nanowires for In-Memory-Computing Applications

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9212585

**Abstract:**

We propose, for the first time, an indium gallium zinc oxide (IGZO)-based 2T1C compute cell (IGZO-cell) for analog in-memory computing. To assess the impact of an IGZO-cell-based array including the periphery on power and accuracy, a PyTorch framework was developed to analytically modeled analog components. The results are reported for a ResNet20 network on the Canadian Institute For Advanced Research-10 (CIFAR-10) benchmark. The state-of-the-art energy efficiency of 15 peta operations per second (POPS)/W including the periphery is achieved by using our proposed IGZO-cell with CMOS compatibility. Finally, it is shown that, with a properly trained neural network model, there is no degradation of test accuracy with 10% device to device variability for the IGZO devices.

IGZO-Based Compute Cell for Analog In- Memory Computing—DTCO Analysis to Enable Ultralow-Power Ai at Edge

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9144248

**Abstract:**

This letter proposes a C-SRAM combining IMC/NMC approaches to be used by a scalar processor as an energyefficient vector processing unit. The proposed circuit is designed with a two-port foundry bitcell and an adjustable form factor to facilitate physical implementation in a SoC. The 4-kB C-SRAM testchip of 128-b words manufactured in 22-nm FD-SOI technology displays a subarray efficiency of 72% as well as an additional computing area of less than 5%. The measurements at 0.85 V and 1 GHz demonstrate an energy efficiency per unit area of 35.6 and 1.48 TOPS/W/mm2 for 8-b additions and multiplications with 3- and 24-ns computing latency, respectively.

A 35.6 TOPS/W/mm2 3-Stage Pipelined Computational SRAM with Adjustable Form Factor for Highly Data-Centric Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9042.pdf

**Abstract:**

This paper presents a systematic design framework for ADC optimization. Our emphasis is on a robust design that is highly repeatable, which is driven by a deep understanding of the behavior of circuit building blocks. A 10 b 500 MS/s single-channel SAR ADC designed in this framework displays uniform performance for inputs up to 2 GHz at state-of-the-art FoM, which demonstrates the power of design based on analytical expressions.

A Tutorial on Systematic Design of CMOS A/D Converters: Illustrated by a 10 b, 500 MS/s SAR ADC with 2 GHz RBW

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9162.pdf

**Abstract:**

This paper presents a low-power and high-linearity noise-shaping SAR ADC that employs a duty-cycled amplifier and a mismatch error shaping technique. The power-efficient duty-cycled amplifier with 18x gain and two passive integrators provide 2nd-order noise shaping to improve in-band noise attenuation. Mismatch error shaping with a two-level digital prediction scheme is used to 1st-order shape the capacitive DAC mismatch errors without sacrificing the input signal range. The proposed ADC is fabricated in 65 nm CMOS technology and achieves 80 dB peak SNDR and 98 dB peak SFDR in a 31.25 kHz bandwidth, leading to a Schreier FoM of 176.3 dB.

An 80dB-SNDR 98dB-SFDR Noise-Shaping SAR ADC with Duty-Cycled Amplifier and Digital-Predicted Mismatch Error Shaping

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9304.pdf

**Abstract:**

In this work, a 10b 400MS/s single-channel SAR ADC is reported. Without an auxiliary sub-ADC, a subranging architecture is proposed, where only one comparator is used with the subsetted capacitive DAC (CDAC), eliminating the mismatch of comparators and saving area. For the subranging process, a partial detect-and-skip (PDAS) switching scheme is proposed, which improves both power efficiency and linearity without delay overhead. In addition, the dynamic logic circuits, including dynamic asynchronous loop (DAL) and dynamic SAR logic (DSL), are improved to reduce the power and logic propagation delay. Fabricated in a 40 nm CMOS process, this single-channel prototype operates at an enhanced sampling rate of 400 MS/s. At Nyquist, 56.4 dB SNDR and 73.1 dB SFDR are achieved. The ADC draws 3.46mW from a single 1.2V supply, leading to a Walden FoM of 16.0fJ/ conversion-step.

A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9204647

**Abstract:**

This paper provides guidelines to design porous silicon layers regarding optimization of small-signal properties in passive structures for RF: insertion loss and cross talk. Results are based on high frequency measurements on 200 mm wafers and electromagnetic simulations up to 40 GHz. Using substrate resistivity below 1 ohm.cm allows the best trade-off with minimized porous silicon thickness.

Influence of Substrate Resistivity on Porous Silicon Small Signal RF Properties

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9186848

**Abstract:**

To enable CMOS compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and fMAX of the transistor. In this paper, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gatemetal process leads to fMAX enhancement up to ~ 50% for devices scaled down to 0.32μm gate lengths. The gate resistance for the Tshaped gate is modelled from S-parameters and validated on various gate field plate geometries. The tradeoff between the gate resistance and parasitic capacitance in GaN HEMTs is highlighted in this case.

Analysis of Gate Metal Resistance in CMOS Compatible RF GaN HEMTs

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9146558

**Abstract:**

In this paper, an ultra-broadband D-band wireless front-end receiver (RX) in 45nm CMOS SOI is proposed. It achieves a Noise Figure of 8 dB, a Gain of 16 dB, a 3 dB bandwidth of 25 GHz, and occupies a compact area of 2 mm2. To our knowledge, for the first time, the required millimeter-wave Local Oscillator signal is generated on-chip. Furthermore, 108 Gb/s data-rate is demonstrated by receiving and demodulating a signal composed of 10×2.16 GHz channels with -40 dBm average power and 64 QAM modulation. With a consumption of 200 mW from a 1-V voltage supply, the proposed RX achieves an energy efficiency of 1.8 pJ/bit

A 108 Gb/S 64-QAM CMOS D-Band Rx with Integrated Lo Generation

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178366

**Abstract:**

In this paper, an ultra-broadband D-band wireless front-end transmitter (TX) in 45 nm CMOS SOI is proposed. Based on channel bonding and 64-QAM modulation, it achieves 84.8 Gb/s data-rate by combining 8×2.16 GHz baseband channels. The eight baseband channels are aggregated at Intermediate Frequency (IF) in two sets of four channels and then up-converted to two adjacent sub-bands at D-band. The required millimeter-wave Local Oscillators (LO) are generated on-chip. The Intermediate Frequency band is 57.96 GHz to 66.66 GHz, and the considered transmission band is from 140.895 GHz to 158.265 GHz. The presented TX integrates two up-converter mixers, two power amplifiers and an on-chip power combiner in addition to the two LO generator with a total DC power consumption of 420 mW from a 1-V voltage supply, and occupies a compact active area of 2.98 mm2.

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