Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199382

**Abstract:**

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-allaround stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

ESSCIRC ESSDERC 2021

Ultrahigh-Density 3-D Vertical RRAM with Stacked Junctionless Nanowires for In-Memory-Computing Applications

stacked nanowires.

scouting logic (scl)

oxram

junctionless (jl) transistors

in-/near-memory computing (imc/nmc)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171855

**Abstract:**

In this letter, a low cost, compact, and systematic method for generating a short pulse and efficiently delivering it to low impedance loads is proposed. The load can be a resistive on-chip or off-chip load, an antenna, or another stage such as a power combiner. The technique is inspired by time-domain reflectometry from a short-circuited termination. The technique is fully compatible with the CMOS technology. To show the feasibility of the idea, two chips are fabricated and tested in a low cost 0.11-μm CMOS process with fT ≈ 80GHz. The full-width at half maximum (FWHM) of the pulses are 6.8 ps and 8.8 ps, and the amplitudes over a 50 load are 0.62 V and 1 V. Either of the chips occupies 1160 × 540μm2 in area.

Reflection-Based Short Pulse Generation in CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205911

**Abstract:**

A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gb/s ultrawideband transceiver fabricated in 28-nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops, one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing is used to control a back-bias-controlled oscillator and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature variations, including skewed process corners. The CR occupies a silicon area of 0.043 mm², locks in less than 1.1 μs, generates an RMS long-term jitter of 6.5 ps, and consumes 1.034 mW while in-lock. This results in an energy value of 0.414 pJ/cycle and a jitter FoM of −224 dB.

A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9255.pdf

**Abstract:**

Silicon and its native oxide SiO 2 are the most commonly used materials in semiconductor device technology. After decades of research in this field, details of the initial oxidation and the subsequent O migration and amorphization are still a subject of interest. In this paper, we present a multiscale modeling approach to investigate the oxidation process of a Si(100) surface. Starting from the adsorption and dissociation of single O 2 molecules, we further extended our investigations towards the initial oxidation of the first Si layer and subse- quent O migration. Finally, we construct a realistic model of a Si/SiO 2 interface consisting of around 5000 atoms. The employed simulation techniques used in this study range from density functional theory (DFT) to density functional based tight binding (DFTB) to classical molecular dynamics (MD).

Multiscale Modeling Study of Native Oxide Growth on a Si(100) Surface

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9152.pdf

**Abstract:**

A ML based framework is presented to predict the formation and structure of defect in amorphous structures, aiming at reducing the computational costs which these studies require. The framework is applied to the prediction of hydroxyl E\' center defects in amorphous silicon dioxide. The results demonstrate a competitive level of accuracy, while being computationally inexpensive, when compared to DFT.

Machine Learning Prediction of Defect Structures in Amorphous Silicon Dioxide

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9266.pdf

**Abstract:**

It is well established that oxide defects are a major threat concerning the reliability of electronic devices. Point defects like the oxygen vacancy and hydrogen related defects like the hydrogen bridge and the hydroxyl-E\' center can trap charges from the Si substrate during operation. Here we present a statistical study of parameters by analyzing 144 defects of each type in amorphous SiO2 . We use density functional theory in conjunction with a hybrid functional to provide a large and accurate dataset of defect parameters such as the relaxation energy or the charge transition level and link them to bias temperature instability in nMOSFET devices.

Statistical Ab Initio Analysis of Electron Trapping Oxide Defects in the Si/SiO2 Network

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9264.pdf

**Abstract:**

This work presents a new method of noise model implementation for circuit simulations, which enables the generation of Lorentzian-type spectra. The importance of Lorentzian noise modeling is explored in contrast to classic 1/f or Random Telegraph Noise (RTN) modeling, in terms of PSD, total noise power, and device-to-device noise variability reproduction, through analysis of experimental data. The Verilog-A modeling methods for both types of Lorentzian noise are demonstrated and validated, using a Lambert-W function charge-based drain current model. Finally, fundamental digital and analog circuits such as the Ring Oscillator are used to showcase the usefulness and applicability of the “VERILOR” model in circuit noise simulations.

VERILOR: A Verilog-A Model of Lorentzian Spectra for Simulating Trap-Related Noise in CMOS Circuits

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9260.pdf

**Abstract:**

This paper presents reliability assessment of basic integrated circuits designed for analog and RF applications based on extensive circuit simulations using the aging compact model, HiCuM-AL v3.0, dedicated to SiGe HBTs. The physic-based aging compact model implemented within HiCuM model is based on trap generation-annihilation mechanisms as well as the Fick hydrogen diffusion law. The model has been validated against results from HBT aging tests under various stress conditions followed by aging model parameter extraction. Due to its extensive use in integrated circuit blocks, different current mirror configurations subjected to mixed-mode stress conditions are studied and analyzed in order to quantify the impact of HC degradation on individual HBTs as well as on overall circuit performances.

Impact of Hot Carrier Degradation on the Performances of Current Mirrors Based on a 55 nm BiCMOS Integrated Circuit Technology

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9230.pdf

**Abstract:**

This paper presents the analog predistortion abilities to linearize power amplifiers, operating both for satellite and mobile applications. A design example is done in Ku-band downlink applications with an integrated reflector-based analog predistortion. The proposed solution is a two cells nonlinear load-based AM/AM and AM/PM generation circuit made in a 130nm BiCMOS technology. The measurements performed for different biasing voltages and at different frequencies result in a gain compensation range between 0 dB and 9 dB and a phase compensation range between 0 and 50°. The size of each cell is 0.2 mm² and its total maximum power consumption is as low as 9 mW

Fully Integrated Reflector-Based Analog Predistortion for Ku-Band Power Amplifiers Linearization

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9234.pdf

**Abstract:**

A broadband 3-stage pseudo-differential SiGe power amplifier, fabricated in an experimental 130 nm SiGe BiCMOS technology with ft/fmax of 470/650 GHz, is presented in this paper. Coupled-line matching networks with optimized impedance ratios are used to maximize bandwidth and output power while maintaing flat power gain and group delay for wireless communications applications. The amplifier provides a maximum small-signal power gain of 17.9 dB and a peak Psat/OP1dB of 6.7/5.2dBm, respectively. The measured small-signal and saturated power 3-dB bandwidth cover 59 GHz (239-298~GHz) and 89 GHz (226-315~GHz), respectively. The DC power consumption is about 417 mW, resulting in a power-added-efficiency of 0.92\\%. This power amplifier has the highest absolute small-signal bandwidth and highest output power in the J-Band for a silicon power amplifier without additional power combining. Without the balun at the input and output, the amplifier provides upto 8.1 dBm and a small-signal gain above 20 dB in an integrated differential circuit.

A 239-298 GHz Power Amplifier in an Advanced 130 nm SiGe BiCMOS Technology for Communications Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9219.pdf

**Abstract:**

This paper introduces a phase shifter based on switched filters for mm-wave 5G MIMO transmitters. It is realized in 22nm FD-SOI CMOS and exploits the use of back-gate biasing. The new approach features strong tolerance to process, voltage and temperature (PVT) variations and thus can maintain low phase error with fine phase tuning capability supporting a large bandwidth. Measurement results show that the 4-bit phase shifter achieves 3.5 degree rms phase error at 28 GHz. The proposed phase shifter can maintain <5 degree of the worst-case rms phase error when operating across 24 to 29.5 GHz resulting in 20.56% fractional bandwidth which is the largest among the published switched-filter phase shifters to date.

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