Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9276.pdf

**Abstract:**

We present a study based on numerical simulations and comparative analysis of recent experimental data concerning the operation and design of FeFETs. Our results show that a proper consideration of charge trapping in the ferroelectric-dielectric stack is indispensable to reconcile simulations with experiments, and to attain the desired hysteretic behavior of the current-voltage characteristics. Then we analyze a few design options for polysilicon channel FeFETs and, in particular, we study the influence of the channel thickness and doping concentration on the memory window, and on the ratio between the polarization dependent, high and low resistance state.

ESSCIRC ESSDERC 2021

Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation

memory window

fets

traps

ferroelectrics

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9185.pdf

**Abstract:**

All-digital millimeter-wave massive multi-user MIMO receivers enable extreme data-rates but require high power consumption. To reduce power consumption, this paper presents the first resolution-adaptive all-digital receiver ASIC that is able to adjust the resolution of the data-converters and baseband processing to the instantaneous communication scenario. The scalable 32-antenna, 65nm CMOS receiver occupies a total area of 8mm2 and integrates ADCs with programmable gain and resolution, beamspace channel estimation, and a resolution-adaptive processing-in-memory spatial equalizer. With 6-bit ADC samples and a 4-bit spatial equalizer, our ASIC achieves a throughput of 9.98Gb/s while being at least 2x more energy-efficient than state-of-the-art designs.

A Resolution-Adaptive 8mm² 9.98 Gb/s 39.7 pJ/b 32-Antenna All-Digital Spatial Equalizer for mmWave Massive MU-MIMO in 65nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9034.pdf

**Abstract:**

We present a hardware accelerator, fabricated in180 nm CMOS, for baseband timing of BLE mesh networks. The timing circuitry augments the BLE physical layer with a new command that enables scalable synchronization and aggressive duty-cycling of mesh nodes for low-power P2P communication. The custom ASIC contains a digital correlator which enables low-latency detection of a BPSK synchronization packet, or syncword. The detected syncword advances the phase of a nonlinear pulse-coupled oscillator, which drives the network to a synchronized state. The accelerator interfaces with the AD9364 software-defined radio via a ZedBoard to make a fully functional node. Duty-cycled multi-hop communication is demonstrated with total power consumption per radio node of less than 1mW while communicating 64-bit 10 MSPS packets

Scalable Digital Synchronizer for Enabling Hardware-Level BLE Mesh Networks Under 1mW

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9288.pdf

**Abstract:**

A new standard cell topology, Dual-Input Pseudo-CMOS (DIPC), for dual-gate Indium-Gallium-Zinc-Oxide (IGZO) thin-film transistor (TFT) technology on flexible substrates is presented. The proposed logic topology is compared with the conventional Pseudo-CMOS in terms of robustness (noise margin), speed performance, power consumption and area usage. This work shows that the back-gate of a TFT can be used as a separate parallel transistor reducing the number of devices in logic gates without compromising the speed and the power. Two 32-bit code generators for RFID transponders with both libraries have been designed and fabricated using n-type only TFTs with a channel length of 5 micrometers. The proposed topology allowed to reduce the number of TFTs by 24% and the chip consumes only 2.2 microwatt of power at 4 kHz clock frequency and 1 V of supply voltage. This work also forecasts that the number of TFTs can be reduced strongly by using the proposed DIPC topology for complex designs such as arithmetic logic units and microprocessors.

Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9165.pdf

**Abstract:**

This work presents a 16mm2 heterogeneous RISC-V SoC composed of a high-performance out-of-order core, energy-efficient in-order core, data-parallel vector accelerator, and systolic array DNN accelerator in low-power Intel 22FFL for general-purpose compute, DNN, and vector workloads. The heterogeneous RISC-V SoC is composed of fully open-sourced components, including a second-generation Berkeley Out-of-Order Machine (BOOM) with a non-speculative mode attached to a Hwacha vector accelerator, a Rocket in-order core attached to a Gemmini systolic array DNN accelerator, as well as a 1MiB L2 cache and off-chip I/Os. Combined, the variety of heterogeneous compute allows for wide programmability while providing up to a 286x improvement in MOPS/W or 282x MOPS improvement over the RISC-V in-order core.

A 16mm² 106.1 GOPS/W Heterogeneous RISC-V Multi-Core Multi-Accelerator SoC in Low-Power 22nm FinFET

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9156.pdf

**Abstract:**

We present Thestral, a 10-core RISC-V chip for energy-proportional parallel computing manufactured in 22nm FD-SOI technology, featuring a control core and a nine-core compute cluster, with specialized units for floating-point (FPU) and integer (IPU) extensions. Each FPU, IPU, and the whole cluster can be independently power-gated with a sub-10 ns power-up sequence, allowing fine-tuning of leakage vs. dynamic power ratio. We achieve up to 42% measured power savings in a low-power, near-threshold operating point (@350 MHz, 0.6V, 25 °C). In a high-performance operating point (@850 MHz, 0.9V, 75 °C), a many-core Thestral may save up to 41% power during memory-bound application phases.

A 10-Core SoC with 20 Fine-Grain Power Domains for Energy-Proportional Data-Parallel Processing Over a Wide Voltage and Temperature Range

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9143.pdf

**Abstract:**

IoT end-nodes require extreme performance andenergy efficiency coupled with high flexibility to deal with theincreasing computational requirements and variety of mod-ern near-sensor data analytics applications. Low-Bitwidth andMixed-Precision arithmetic is emerging as a trend to addressthe near-sensor analytics challenge in several fields such aslinear algebra, Deep Neural Networks (DNN) inference, andon-line learning. We present Dustin, a fully programmableMultiple Instruction Multiple Data (MIMD) cluster integrating16 RISC-V cores featuring 2b-to-32b bit-precision instruction setarchitecture (ISA) extensions enabling fine-grain tunable mixed-precision computation. The cluster can be dynamically configuredin Vector Lockstep Execution Mode (VLEM), turning off all IFstages except one, reducing power consumption by up to 38%with no performance degradation. The cluster, implemented in65nm CMOS technology, achieves a peak performance of 58GOPS and a peak efficiency of 1.15 TOPS/W.

A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9058.pdf

**Abstract:**

This paper presents circuit monitoring, reviewing different classes of silicon monitoring solutions, the specificity of each class and where they best fit in the life-cycle of circuit design. Circuit monitoring for Silicon versus Computer-Aided- Design (CAD) calibration. In-Die test and In-Field compensation using Adaptative Voltage Scaling (AVS) or Adaptative Body-Bias (ABB) or both are discussed. Illustrations of Silicon measurement or CAD simulation analysis from 40nm CMOS general purpose, 28nm FD-SOI automotive are exposed.

Circuit Monitoring Across Design Life-Cycle in 28nm FD-SOI and 40nm Bulk CMOS Technologies

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9344.pdf

**Abstract:**

InGaAs is an attractive material for high-speed, high-frequency electronics and ultra-low-noise applications. This paper discusses a number of interesting device physics in nanoscale InGaAs FinFETs of relevance to the development of electronics based on other material systems: excess off-state current due to band-to-band tunneling and a parasitic lateral bipolar transistor effect, ballistic mobility and injection velocity, as well as a new technique to extract the charge-control relationship in the presence of severe gate oxide trapping.

Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9015.pdf

**Abstract:**

The subject of the paper is substrate capacitance modeling for MOSFET-based RF switches on high-ohmic silicon substrates. Microstrip line computational models are applied for calculating the capacitance. It is proposed to use inverted microstrip line model for the flip-chip IC mounting configuration. The model-to-hardware correlation has been demonstrated on a prototype switch IC fabricated in a dedicated 130nm bulk- CMOS technology. The calculated switch RF breakdown voltages (serving as an indicator for the substrate capacitance) of 56V and 54.8V was measured to be 55.4V and 51.4V for the wire-bonded and flip-chip ICs respectively.

Model of Substrate Capacitance of MOSFET RF Switch Inspired by Inverted Microstrip Line

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9207.pdf

**Abstract:**

With rising demand for higher frequency system-on-chip MEMS, accuracy in the modelling and design phase becomes increasingly important. The impact of mechanical anisotropic layers on the acoustic band gap formation in a CMOS back-end-of-line Bragg mirror is studied by analytic and finite element approaches. In particular the influence of anisotropic monocrystalline copper sheets, with varying crystal orientations, is investigated for monolithic high-Q MEMS resonator confinement. It is shown that for a mechanical FinFET resonator in the front-end-of-line multiple resonant frequencies can coexist on the same wafer, depending on the spatial extents of the device. All of which need to be accommodated by a broadband mechanical band gap in the back-end-of-line which is demonstrated for different anisotropic copper crystal orientations.

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