Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9056.pdf

**Abstract:**

RRAM-based compute-in-memory (CIM) has shown great potentials for deep neural network inference. Prior works generally used off-chip write-verify for tightening resistance distributions and off-chip ADC references to fine-tune partial sum quantization, which may be unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate ADC offsets to guarantee CIFAR-10 accuracy of &gt;90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W on VGG-8 network.

ESSCIRC ESSDERC 2021

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

adc reference generation

write-verify

compute-in-memory

rram

non-volatile memory

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9056.pdf

**Abstract:**

RRAM-based compute-in-memory (CIM) has shown great potentials for deep neural network inference. Prior works generally used off-chip write-verify for tightening resistance distributions and off-chip ADC references to fine-tune partial sum quantization, which may be unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate ADC offsets to guarantee CIFAR-10 accuracy of >90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W on VGG-8 network.

technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171283

**Abstract:**

This work presents a simplex and a full duplex digital communication interface that enhance the energy efficiency of chip-to-chip digital communication in low speed low power systems. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5^10-12. The simplex and full duplex interfaces achieve an energy consumption of 0.38pJ/b and 1.2pJ/b respectively. The simplex interface achieves a power reduction of 2× to 27× compared to conventional LVCMOS for data rates from 10kb/s to 50Mb/s. The full duplex interface achieves a power reduction of 5× to 11× for data rates from 100kb/s to 50Mb/s.

A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9160876

**Abstract:**

The data rate-times-distance product in mm-wave dielectric waveguide (DWG) communication links is usually limited by waveguide dispersion. This letter presents the DWG\'s baseband impulse response in the context of a homodyne receiver and introduces a continuous-time linear equalizer able to minimize such dispersion. The desired transfer function is implemented with inverter-based transconductance cells. The simulation and measurement results at 10-Gbps data rate show eye-opening improvement at two distances (10 and 15 m) and carrier frequencies (140 and 160 GHz). The equalizer occupies 80 × 32 μm2 in GLOBALFOUNDRIES 22-nm FD-SOI.

A 10-Gbps Continuous-Time Linear Equalizer for mm-Wave Dielectric Waveguide Communication

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205866

**Abstract:**

The use of new materials with advanced properties has become mandatory to meet the needs for higher electronics performance at reduced power. Topological insulators (TIs) possess highly conductive topologically protected edge states which are insensitive to scattering and thus suitable for energy-efficient highspeed devices. Here,we evaluate the subband structure in a narrow nanoribbon of 1T molybdenumdisulphide using an effective k·p Hamiltonian. Highly conductive topologically protected edge modes whose energies lie within the bulk band gap are investigated on equal footing with traditional electron and hole subbands. Due to the interaction between the edge modes at opposite sides, a small gap in their linear spectrum opens up in a narrow nanoribbon. This gap is shown to sharply increase with the perpendicular out-of-plane electric field, in contrast to the behavior in a wide nanoribbon with negligible edge modes’ interaction. This increase leads to a rapid decrease in the ballistic nanoribbon conductance and current with the electric field, which can be used for designing molybdenum disulphide nanoribbon-based current switches.

Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T\' Phase

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9210837

**Abstract:**

An analytical model for back bias capability including interface traps, quantum confinement, short channel effects is developed, which is in excellent agreement with TCAD simulations and measurements. The derived expressions facilitate the accurate assessment of interface trap impact on variability and also benefit the configuration of dynamics back bias for aging compensation, thereby fully leveraging the UTBB FDSOI technology.

Analytical Model for Interface Traps Dependent Back Bias Capability and Variability in Ultrathin Body and Box FDSOI MOSFETs

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9186799

**Abstract:**

In this study, a consistent analytical chargebased model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-numberfluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated-Mobility Fluctuation

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9184253

**Abstract:**

A charge-based macromodel for small-signal ac and transient analyses of organic thin-ﬁlm transistors (TFTs) is presented. Due to the comparatively small charge- carrier mobility in organic TFTs, the dynamic behavior of the gate-ﬁeld-induced carrier channel is greatly affected by the frequency of the applied gate–source and drain–source voltages. The model presented here is, therefore, based on the transmission-line model and shown to reproduce the results of frequency-dependent admittance measurements and numerical simulations of the transient switching behavior of organic TFTs fabricated in the staggered architecture with good accuracy. The model has been implemented in the hardware description language Verilog-A.

Macromodel for AC and Transient Simulations of Organic Thin-Film Transistor Circuits Including Nonquasistatic Effects

This keynote is describing the evolution of Artificial Intelligence (AI) adoption to the Edge for maximizing Data processing at the User experience level to treat as much as possible data analysis without saturating Internet traffic and Cloud data centers. Evolution of Neural Network (NN) computing through progressive usage of In Memory Computing (IMC) is also described. A few examples of Artificial Intelligence at the Edge are also commented. We then describe how at ST, we address competitive solutions for Edge AI thanks to differentiated FD-SOI CMOS technology, Phase Change Memory (PCM) embedded memory integration and advanced NN and IMC design solutions.

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Next from ESSCIRC ESSDERC 2021

A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

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A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area

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