United States

Abstract Body: Background. β-Ga2O3 has been actively studied for power electronics, RF devices, etc. Among various device topologies, fin-structures are particularly attractive since they enable the RESURF effect, which is key in designing high-field electronics and enhancement-mode transistor operation1,2. Fin-structures have been successfully employed in demonstrating record-setting devices in β-Ga2O33,4. However, we also observed in these devices that a “waist” tends to develop in the middle of a fin thus current flow can be severely pinched by “narrowed waist”. Here, we report what has been learned to date on fin-waist formation during ICP reactive ion etching (RIE). Experiments. The fin/trench arrays were fabricated on single-crystal β-Ga2O3 substrates with 2 orientations: (010) and (001). Hard masks of Pt were patterned by EBL for fin/trench widths less than 1 μm and optical lithography for wider ones. Definitions of dimensional parameters for fin, trench, fin waist and waist narrowing are illustrated in Fig.1. The dry etch parameters were fixed at 350 W ICP power, 20 W RIE power, 5 mTorr, 20C with 35 sccm BCl3 and 5 sccm Ar. Prior to SEM, the etched samples were soaked in HCl and/or HF to remove etch damage/residue. This dry+wet etch condition has rendered consistently rectangular-shaped single fins on (001) β-Ga2O3 with a fin height/width aspect ratio (AR) up to 9 and used in our reported devices3. Fin-waist dependence on the fin orientation and AR of fins/trenches. Arrays of fins were etched on (001) β-Ga2O3 with fin orientation varied. The fin width was varied from 0.15 to 8 μm, the trench width was varied from 1 to 8 μm, and the fin/trench depth was varied from 1.1 to 2 μm, which corresponds to a fin AR of 0.2-9 and a trench AR of 0.5-1.3. Upon examining cross-sections of these fins/trenches under SEM (Figs. 2-4), we discover following trends: 1) all outermost sidewalls of fin arrays and single fins appear to be vertical, while inner sidewalls all show waist; 2) there is no noticeable dependence on fin orientation; 3) waist narrowing increases from 50±10 nm for a trench AR of 0.5 to 200±10 nm for a trench AR up to 1.3, while appears nearly independent of fin width; and 4) wet etch worsens waist narrowing. Fin-waist dependence on the substrate orientation. Similar trench etching experiments were applied to (010) substrates, given their popular use in device development. Example cross-section SEM images are shown in Fig. 5. Though the ranges of fin/trench geometric parameters are slightly different from the ones explored on the (001) β-Ga2O3, the trends observed are largely consistent across different substrate orientations. Discussions. To advance fin-based device performance, it is essential to increase filling factor of fins with respect to entire area occupied by devices on wafer; the preferred trench AR is &gt;1. Under the present ICP-RIE etch condition, waist narrowing is minimal for a low trench AR; but low trench AR implies a low filling factor of current-carrying fins. Waist narrowing is tolerable for fat fins, but the resultant fins can suffer from severe waist narrowing for large-AR trenches and narrow fins (Fig.6) thus detrimental to realizing smooth current flow in devices. Based on our observations, we hypothesize that in trenches with a high AR, a combination of poor sidewall passivation and ion/electron redistribution can result in appreciable lateral etching thus forming waist in fins or bowing of sidewalls. Similar effects were widely observed in other material systems, and improved passivation of sidewalls and neutralization of charges on sidewalls are common tactics to suppress bowing. Ongoing studies are undertaken to curb this undesirable waist narrowing. 1Hu, et al, EDL, 39, 869(2018). 2Li, et al, TED, 67, 3954(2020). 3Li, et al, IEDM, 270(2019). 4Li, et al, EDL, 41, 107(2020). * This work is in part supported by AFOSR Center of Excellence: ACCESS (FA9550-18-1-0529). CNF uses are partly supported by NSF NNCI-2025233.

EMC 2021

Fin-Waist Formation in β-Ga2O3 Fin Arrays Defined by ICP-RIE

gallium oxides

finfet

dry etching

icp-rie

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
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* Educational Events

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ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





Abstract Body: Background. β-Ga2O3 has been actively studied for power electronics, RF devices, etc. Among various device topologies, fin-structures are particularly attractive since they enable the RESURF effect, which is key in designing high-field electronics and enhancement-mode transistor operation1,2. Fin-structures have been successfully employed in demonstrating record-setting devices in β-Ga2O33,4. However, we also observed in these devices that a “waist” tends to develop in the middle of a fin thus current flow can be severely pinched by “narrowed waist”. Here, we report what has been learned to date on fin-waist formation during ICP reactive ion etching (RIE). Experiments. The fin/trench arrays were fabricated on single-crystal β-Ga2O3 substrates with 2 orientations: (010) and (001). Hard masks of Pt were patterned by EBL for fin/trench widths less than 1 μm and optical lithography for wider ones. Definitions of dimensional parameters for fin, trench, fin waist and waist narrowing are illustrated in Fig.1. The dry etch parameters were fixed at 350 W ICP power, 20 W RIE power, 5 mTorr, 20C with 35 sccm BCl3 and 5 sccm Ar. Prior to SEM, the etched samples were soaked in HCl and/or HF to remove etch damage/residue. This dry+wet etch condition has rendered consistently rectangular-shaped single fins on (001) β-Ga2O3 with a fin height/width aspect ratio (AR) up to 9 and used in our reported devices3. Fin-waist dependence on the fin orientation and AR of fins/trenches. Arrays of fins were etched on (001) β-Ga2O3 with fin orientation varied. The fin width was varied from 0.15 to 8 μm, the trench width was varied from 1 to 8 μm, and the fin/trench depth was varied from 1.1 to 2 μm, which corresponds to a fin AR of 0.2-9 and a trench AR of 0.5-1.3. Upon examining cross-sections of these fins/trenches under SEM (Figs. 2-4), we discover following trends: 1) all outermost sidewalls of fin arrays and single fins appear to be vertical, while inner sidewalls all show waist; 2) there is no noticeable dependence on fin orientation; 3) waist narrowing increases from 50±10 nm for a trench AR of 0.5 to 200±10 nm for a trench AR up to 1.3, while appears nearly independent of fin width; and 4) wet etch worsens waist narrowing. Fin-waist dependence on the substrate orientation. Similar trench etching experiments were applied to (010) substrates, given their popular use in device development. Example cross-section SEM images are shown in Fig. 5. Though the ranges of fin/trench geometric parameters are slightly different from the ones explored on the (001) β-Ga2O3, the trends observed are largely consistent across different substrate orientations. Discussions. To advance fin-based device performance, it is essential to increase filling factor of fins with respect to entire area occupied by devices on wafer; the preferred trench AR is >1. Under the present ICP-RIE etch condition, waist narrowing is minimal for a low trench AR; but low trench AR implies a low filling factor of current-carrying fins. Waist narrowing is tolerable for fat fins, but the resultant fins can suffer from severe waist narrowing for large-AR trenches and narrow fins (Fig.6) thus detrimental to realizing smooth current flow in devices. Based on our observations, we hypothesize that in trenches with a high AR, a combination of poor sidewall passivation and ion/electron redistribution can result in appreciable lateral etching thus forming waist in fins or bowing of sidewalls. Similar effects were widely observed in other material systems, and improved passivation of sidewalls and neutralization of charges on sidewalls are common tactics to suppress bowing. Ongoing studies are undertaken to curb this undesirable waist narrowing. 1Hu, et al, EDL, 39, 869(2018). 2Li, et al, TED, 67, 3954(2020). 3Li, et al, IEDM, 270(2019). 4Li, et al, EDL, 41, 107(2020). * This work is in part supported by AFOSR Center of Excellence: ACCESS (FA9550-18-1-0529). CNF uses are partly supported by NSF NNCI-2025233.

technical paper

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Abstract Body: The integration of plasmonic materials with emitters and optoelectronic devices allows for remarkable enhancement and improved understanding of light-matter interaction. Previous approaches to plasmonic integration rely on the noble metals to achieve a plasmonic response near the metal’s plasma frequency, limiting plasmonic devices to the near-infrared and visible wavelength range. The noble metals offer strong confinement but with the possibly of greater loss.[1] Since emitters in the near-infrared and visible wavelength ranges already have high optical efficiencies, it is difficult to increase that efficiency with the introduction of a plasmonic material. However, the mid-infrared has few highly efficient light emitting materials.[2] Emission from mid-infrared materials can be significantly enhanced when coupled with a plasmonic material and thus have a strongly enhanced efficiency. The integration of a noble metal in the near-field of an emitter is often incompatible with the electronic requirements of the active device, compromising the device architecture and significantly limiting possible emission enhancement.[3] Each of these drawbacks conspire to limit the design flexibility and potential performance of polylithically-integrated metal-based optoelectronic devices. Molecular beam epitaxy allows for the engineering of so-called “designed metals” for a monolithic all-epitaxial integration of a plasmonic material and active device in the mid-infrared.[4] Previously we have shown the first all-epitaxial integration of a plasmonic “designer metal” and emitter to produce a cavity-enhanced light-emitting diode (LED).[5] Experimental electroluminescence showed a strong enhancement of emission at the peak wavelength, increasing by a factor of 5.6x when compared to a control LED. The device with the plasmonic virtual substrate showed upper hemisphere powers of 1.45 μW at 300 K, comparable to state-of-the-art mid-infrared LEDs at the same wavelength.[6] In order to increase the efficiency of the cavity-enhanced LEDs, we are integrating our emitters into an AlInAsSb/InAs/AlInAsSb double heterostructure design with a tunnel junction to increase efficiency.[7] The cavity-enhanced LED design was optimized using rigorous coupled-wave analysis. Further simulations and characterization of the double heterostructure cavity-enhanced LED are underway and will be presented at the conference. This work was supported by the National Science Foundation (NSF) under grant EECS-1926187 and performed at the Texas Nanofabrication Facility, supported by NSF grant NNCI-2025227. [1] J. B. Khurgin and A. Boltasseva, MRS Bulletin, 37, 768, (2012). [2] D. Jung, et al., J. Opt., 19, 123001 (2017). [3] J. B. Khurgin and G. Sun, Nat. Photonics, 8, 468 (2014) [4] S. Law, et al., Opt. Express (2012). [5] A.F. Briggs, et al., Optica, 7, 1355 (2020). [6] Boston Electronics, IoffeLED, Optically immersed 7.0 µm optically pumped LED in heatsink optimized housing, OPLED70Sr datasheet. [7] A. J. Muhowski et al., 2020 IEEE Research and Applications of Photonics in Defense Conference (RAPID), (2020).

Enhanced Double Heterostructure Infrared LEDs Using Monolithically Integrated Plasmonic Materials

Abstract Body: Silicon photonics require a reliable integrated light source to be a viable technology. While heterogeneous integration techniques such as wafer bonding III-V on silicon has proven successful, dramatic cost reductions can be achieved through direct growth of III-V on silicon. This presents numerous challenges to material quality due to mismatches in lattice constant, coefficient of thermal expansion, and crystal symmetry. Even so, decades of work developing defect filtering buffers paired with defect-tolerant quantum dot (QD) active regions have yielded lasers with satisfactory reliability at room temperature, however laser lifetimes at elevated temperatures remain insufficient for commercial applications. We have recently uncovered a source for lagging performance in InAs QD lasers on silicon, namely misfit dislocations (MDs) that lie along the upper and lower boundaries of the active region and act as potent non-radiative recombination centers. We have proposed that these MDs form not due to lattice mismatch in the active region, but instead form by an alternative mechanism based on (1) tensile thermal strain that builds in the AlGaAs cladding layers during cooldown after growth and (2) pinning of threading dislocations (TDs) in the InAs QD active region. TDs, which are mobile in the cladding layers above ~300 °C, glide to relieve the thermal tensile strain in these layers. The TD segment passing through the active region would ideally glide with the segment in the cladding, but as QDs act as powerful pinning sites, glide is prohibited under these low stress conditions. It follows then that MDs will form at both the upper and lower boundaries between the cladding and active region if both cladding layers are above critical thickness due to thermal strain. To solve this, we insert strained indium-alloyed “trapping layers” (TLs) to displace formation of these MDs away from the active region. Unlike the active region, these layers do not contain QDs, but they can still pin TDs in the low stress environment encountered during cooldown because natural compositional fluctuations in the indium-alloyed TLs generate sufficiently large in-layer stress fluctuations. In lasers with TLs, MDs are no longer adjacent to the active region, so their supply of minority carriers is sharply reduced, benefiting not only initial laser performance but also laser reliability since this reduces recombination-enhanced dislocation climb, which we have observed to be a significant source of laser degradation. Initial performance improvements over baseline include median threshold current reduced by half, median slope efficiency increased by over 50%, and median output power increased by over 3×. Thermal performance is also greatly improved with the threshold characteristic temperature, T0, increased from 70 K in baseline lasers to 100 K in TL lasers, indicating their lasing threshold is less sensitive to temperature. Initial laser aging experiments reveal that TLs dramatically enhance the reliability of InAs QD lasers on silicon. After aging for 1200 h at 60 °C at approximately 2× initial 60 °C threshold current, TL lasers have a median threshold current increase of just 3%, far lower than the 56% increase for baseline lasers, lower than the 19% increase of our previous record lifetime InAs QD lasers on silicon under comparable conditions, and even lower than the 11% median threshold increase of QD lasers on GaAs substrates. We suspect that the TL lasers’ lower degradation rate compared to lasers on GaAs, despite their much lower TD density, is due to the higher thermal conductivity of the silicon substrate which reduces the active region temperature during operation. Overall, these reliability results provide a clear path forward toward reliable monolithically integrated light sources for silicon photonics.

High-Reliability InAs QD Lasers on Silicon Through Misfit Dislocation Trapping Layers

Abstract Body: InGaAs is an ideal material for near-infrared (near-IR) photodetection at telecommunications wavelengths. Its direct band gap offers strong absorption and is tunable by varying the alloy composition, making InGaAs versatile for such applications. However, most commercial devices based on this material require InP substrates, which are costly and difficult to process. Moreover, the In content of the InGaAs layer is limited by the requirement for lattice matching.[1] Nanowires are a promising avenue for heteroepitaxy of InGaAs and InAs on common substrates like Si and GaAs, and offer several performance advantages over bulk devices.[2] For example, their thin, anisotropic geometry enables devices to benefit from fast carrier collection and polarization-dependent absorption, making them suitable for fast and efficient multiplexed applications.[3] Nanowires also allow for a significant reduction in the amount of scarce materials, such as In, required to make a device. Typically, nanowires are grown vertically, perpendicular to the substrate, but vertical nanowires are notoriously difficult to incorporate into devices, and a horizontal configuration is often preferred. Recently, horizontal networks of high-quality In(Ga)As nanowires have been demonstrated by growing them on top of GaAs nanomembrane buffers using selective-area epitaxy on III-V substrates.[4,5] In this work we investigate the growth of horizontal In(Ga)As nanowire networks on GaAs substrates by molecular beam epitaxy. An epitaxial GaAs buffer nanomembrane is grown on the substrate to ensure high crystal quality In(Ga)As. Different crystallographic orientations are investigated. For growth on (111)B GaAs substrates, we demonstrate InGaAs nanowire networks positioned atop high aspect ratio GaAs nanomembranes. We show that the In content of the nanowires can be tuned up to 50% of the group III component by controlling growth conditions, but that pure InAs nanowires are not achievable.[6] Next, we demonstrate InAs nanowires grown on low-aspect ratio GaAs nanomembrane on (100) GaAs substrates. The nanowires grow conformally on the nanomembranes, which are dominated by (111) facets, and pure InAs can be achieved with just a narrow intermixed region near the interface. We compare the nanowires on each of these crystallographic orientations, highlighting their advantages for different applications. Finally, we present preliminary electrical characterization data from basic photodetector devices based on these nanowires. We compare nanowires of different lengths and widths and characterize the photoconductive response for both single nanowires and ensembles in an array. Insights from these preliminary results will guide design choices for future photodetector architectures based on these nanowires. 1 R. LaPierre et al., J. Phys. D: Appl. Phys. 50 (2017) 2 C. L. Tan et al., Nanophotonics. 7 (2018) 3 A. Dorodnyy et al., IEEE J. Sel. Top. Quant. Electr. 24 (2018) 4 M. Friedl et al., Nano Lett. 18 (2018) 5 F. Krizek et al., Phys. Rev. Mat. 2 (2018) 6 M. Friedl et al., Nano Lett. 20 (2020) Funding from Swiss National Science Foundation, NCCR QSIT

Scalable III-V Nanowire Networks for IR Photodetection

Abstract Body: Ga-assisted self-catalyzed epitaxial growth and demonstration of Te-doped axial GaAsSbN NW-based Schottky barrier photodetector on p-Si (111) in the near-infrared region is reported. The successful growth of improved dilute nitride quaternary GaAsSbN (Te) NWs in axial configuration was achieved by stringent control on NW nucleation conditions, NW stem growth, and exposure of N-plasma on NW growth. Planar defect-free structures were realized with room temperature photoluminescence (PL) characteristics, revealing reduced N-induced point defects and non-radiative recombination centers. N incorporation in the dilute nitride NWs was ascertained from PL and Raman spectral mode shifts and shapes and weak temperature-dependent PL peak energy. The advantage of Te-doping in dilute nitride NW using a GaTe captive source in the compensation of point defects is demonstrated, as evidenced by a significant improvement in PL characteristics, Raman mode shifts, and spectral shape with improved photodetector device performance relative to intrinsic dilute nitride NWs. Te-doped GaAsSbN NW Schottky based photodetectors have been demonstrated on both single and ensemble configurations yielding responsivity of 5 A/W at 860 nm and 3800 A/W at 1100, respectively. Detectivity of 3.2x1010 Jones was achieved on the Te-doped ensemble NW device. This work showcases rich prospects for engineering bandgap in the near-infrared region for telecommunication wavelength applications using GaAsSb alloy system.

Epitaxial GaAsSbN (Te) NWs for Near-Infrared Region Photodetection Application

Abstract Body: We report on a systematic investigation of the effect of tellurium (Te)-doping on the morphological, optical, and electrical properties of the GaAsSb nanowires (NWs) grown by self-catalyzed molecular beam epitaxy and realization of the ensemble NW photodetector (PD). Qualitative assessment of Te-incorporation in the NWs was made from the structural, optical, and electrical properties, whereas the quantitative assessment was made based on the dark I-V simulations. The single nanowire I-V characterization demonstrated a significant reduction in turn-on voltage with doping. High-resolution transmission electron microscopy image and the selected area electron diffraction patterns of n-GaAsSb NWs revealed the defect-free single-crystal zinc-blende crystal structure. The compositional homogeneity of the NWs is attested by the extended plateau in the energy-dispersive X-ray spectroscopy line scan. An ensemble PD fabricated using n-GaAsSb NWs demonstrated a wide spectral range with the longer wavelength cutoff at ~1.2 µm, with the figure of merits namely, responsivity in the range of 580- 620 A/W and detectivity of 3x 1012 Jones. Low-frequency noise (LFN) spectroscopy revealed the generation-recombination noise being the dominant noise source in the Te doped GaAsSb NWs.

A Te Doped GaAsSb Ensemble Nanowire Photodetector for Near-Infrared Application

Abstract Body: Abstract: Ultrawide Bandgap AlxGa1-xN channel metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) are promising candidates for high-power, high-temperature harsh environment applications. In our recent reports on Al0.4Ga0.6N-channel MOSHFETs with high-k ZrO2 and Al2O3 gate-dielectrics we found that, these dielectrics introduce negative fixed charges (Qox) as high as 1-3×1013 cm-2 depleting 2DEG density of 2×1013 cm-2 causing a positive shift of threshold voltage (VTH) compared to that for HFET (no gate dielectric). This is an important step toward realizing enhanced (E-) mode MOSHFET. Our data show that, ZrO2 possesses higher Qox resulting in stronger positive VTH shift in devices, while devices with Al2O3 demonstrate lower gate leakage. In this work we use stack of ZrO2/Al2O3 to fabricate MOSHFETs. E-mode device was realized using ZrO2/Al2O3 combined with gate recess. To separate effects of dielectric charges and damage from recess process on device performance depletion (D-) mode and E-mode devices were fabricated on the same wafer. Temperature dependent VTH instability of these MOSHFETs were studied and potential mechanism for this VTH instability is discussed. Experimental: The pseudomorphic device structure was grown using metalorganic chemical vapor deposition on a AlN/sapphire template. A graded composition (AlxGa1-xN, x=1-0.4) back barrier was grown to reduce internal stress and improve gate control in the devices[i], [ii] while the top 20 nm graded n-AlxGa1-xN (x from 0.6 to 0.3) was grown to facilitate ohmic contacts. The contact resistance was as low as 1.7 Ω-mm and the 2DEG sheet resistance was ~1900 ohm/sq. Device processing details published elsewhere.[iii] The fixed gate-length LG ≈ 2.0 μm, source to drain spacing, LSD=6 μm, were used for regular devices with 15 μm channel width, while for precise C(V,T,f) measurements we use a test structure with gate area 200x80 μm2 . Results and discussion: The combination of gate recessing and ZrO2/Al2O3 stack resulted in VTH shift of +12.2 V from D to E-mode device. The peak DC currents for D and E-mode devices were found to be 1.1 A/mm and 0.48 A/mm respectively at gate voltage +12 V while in the pulse mode it was 1.3 A/mm and 0.53 A/mm. The gate leakage current in both D and E-mode MOSHFETs is suppressed by ~3 orders of magnitude compared to that of MOSHFETs using singe Al2O3 or ZrO2 layer. ON/OFF ratio as high as 3×108 was achieved which is higher than ~2 orders of magnitude than that for Al2O3 or ZrO2. Temperature dependent VTH and gate leakage study was performed on the fabricated MOSHFETs. It has been found that, from RT to 150 °C there is VTH shift of + 1.7 V and -2.9 V for D- and E-mode MOSHFETs respectively. The VTH shift for similar device having Schottky gate HFET was found to be significantly smaller, +0.2 V which indicates that the VTH shift in MOSHFETs is mainly due to the charges in dielectric or at dielectric-barrier interface. In the E-mode devices, the effective channel mobility (µ) and VTH was additionally affected by radiative defects introduced during gate-recess. µ in D-mode devices decreases with temperature while it increases for the E-mode devices. Temperature dependent interface state density (DIT(T)) and Qox (T) were estimated using frequency- dependent C-V measurements. Our analysis show that in D-mode device, Qox(T) dominates over DIT(T). These fixed negative charges (Qox) deplete the channel giving a total VTH shift of +1.7 V. The extracted SS values of 99 mV/decade (D-mode) and 134 mV/decade (E-mode) indicate an increased density of DIT at the recessed interface in E-mode device. In E-mode, the DIT value is comparable to Qox, thus compensating the temperature effect on Qox and making the VTH more negative. [i]) G. Simin et al., Jpn. J. Appl. Phys., 40, L1142 (2001). [ii]) C. Ren et al., J. Semicond. 36, 014008-1 (2015). [iii]) S. Mollah et al., Appl. Phys. Express. 14, 014003 (2021).

Study of Temperature Effect on Performance of Ultrawide Bandgap Al0.4Ga0.6N-Channel Depletion and Enhancement Mode MOSHFETs with ZrO2/Al2O3 Gate Insulator

Abstract Body: As silicon technology reaches its practical and theoretical limit, III-nitride materials offer a promising alternative to maintain the growing demand for high power electronic devices. Current GaN devices already show promising results, offering higher breakdown voltages and reduced on resistances compared to their silicon predecessors. However, these devices are still limited by the classical Baliga figure of merit (BFOM). In order to surpass the BFOM, novel device geometries have been introduced such as the superjunction (SJ). The concept of the SJ has been demonstrated in silicon, with devices such as CoolMOS which have surpassed the BFOM. To date, there are no demonstrations of III-nitride SJs in the literature. In order to achieve III-nitride SJs, there are several research barriers to address. First, the necessity for alternating, lateral n- and p-type doping regions with zero net charge. The inherent polar doping selectivity of GaN can be used to achieve the doping scheme for a lateral GaN p/n junction. Oxygen, which unintentionally incorporates into N-polar GaN at levels >1019 cm-3, acts as the n-type dopant, whereas Ga-polar GaN does not readily incorporate oxygen. Accordingly, lateral polarity junctions (LPJs) with alternating domains of O doped N-polar and Mg doped Ga-polar GaN have been fabricated to realize lateral p/n junctions. Second, the proper doping profiles must be attained in the N- and Ga-polar domains for SJ operation. For drift regions, the n-type doping in the N-polar domain (and p-type doping in Ga-polar domain) must be reduced to ~1017 cm-3 for micron wide domains. By implementing the chemical potential control (CPC) framework, MOCVD process conditions were designed in order to decrease the oxygen concentration by increasing the growth supersaturation. This led to a reduction in oxygen from >1019 cm-3 to low 1017 cm-3. Third, due to the difficulty of making reliable Schottky contacts to the N-polar surface, the alternating Schottky/ohmic contacts on a typical superjunction are replaced with alternating p+/n- junction (N-polar) and p+/p- junctions (Ga-polar). In this direction, a N-polar p/n junction with rectifying behavior comparable to a Ga-polar p/n junction was achieved. Finally, the growth of a GaN LPJs must exhibit N-/Ga-polar domains with a smooth surface and equal growth rates. It is understood that supersaturation can be used to control the surface morphology, relative growth rates, and defect incorporation of the domains. However, the high supersaturation required to realize the necessary doping profile for SJ operation contradicts the intermediate supersaturation conditions required to obtain a smooth surface morphology and equal domain growth rates. It must be noted that high supersaturations result in low O N-polar dominated growth, and low supersaturations in Ga-polar dominated growth. To overcome these anticorrelated requirements, we demonstrate a supersaturation modulated growth (SMG) where the V/III ratio, and thus supersaturation, was modulated between low and high values. A GaN LPJ with a smooth surface and equal domain heights, with the necessary doping profile is hence demonstrated.

Development of III-Nitride Superjunctions

Abstract Body: Gallium nitride (GaN) has been considered as a promising candidate for power electronic devices due to its wide bandgap (3.4 eV), high critical electric field (3 MV/cm), and high electron mobility (>1000 cm2/V s). As a key parameter to evaluate the performance of power devices, Baliga’s figure of merit (BFOM) of GaN is more than 500X higher than silicon (Si) and 3X higher than silicon carbide (SiC) [1]. Vertical GaN PN diode with 5kV breakdown voltage (VBR) has been demonstrated [2]. Although tremendous progress has been made in the past few years, achieving vertical GaN power devices with VBR of 10-20 kV remains challenging. Epitaxy of high-quality GaN films with a thick drift layer, low controllable doping, and high mobility is required to advance the field. In this work, the effects of increasing GaN growth rate on the impurity incorporation, charge compensation, surface morphology, and transport properties are systematically studied. Under optimized MOCVD GaN growth condition, high-quality GaN films with controllable low net charge concentration (Nd-Na) at 4×1015 cm-3 was demonstrated. Secondary ion mass spectroscopy (SIMS) measured [Si] and Nd-Na as a function of SiH4 flow rate was investigated. The compensation level at (4.8±1.0)×1015 cm-3 was extracted from the intercept of Nd-Na vs. SiH4 flow rate. Based on the capacitance-voltage (CV) and SIMS analysis, the background [C] level was at ~ 7×1015 cm-3 (SIMS detection limit). Deep level transient spectroscopy / deep level optical spectroscopy (DLTS / DLOS) results show total electron trap concentration at ~2.5×1015 cm-3, mainly from carbon-related deep level defects. These high-quality GaN films were grown with a typical MOCVD GaN growth rate of 2 µm/hr. MOCVD GaN epitaxy with fast growth rate at 5.2 µm/hr was achieved via increasing TMGa flow rate. With a controllable Nd-Na at 1.5×1016 cm-3, the SIMS measured [C] was at 2×1016 cm-3, which is significantly increased as compared to the films grown at lower growth rates. Atomic force microscope (AFM) imaging on GaN surface shows smooth morphology with step-flow growth mode and RMS of 0.647 nm (10x10 μm scan area). The Mn incorporation from the semi-insulating ammonothermal GaN substrate into epilayer was observed from SIMS measurement. Controlled experiments show that Mn incorporation rate into epilayer is highly related to the film growth rate, sharing similar characteristics as Fe impurity. Quantitative SIMS revealed that both Mn and Fe incorporation can be suppressed with faster growth rates. Room temperature Hall measurements of GaN films show that electron mobility decreases from 852 cm2/Vs to 604 cm2/Vs (n~1.5x1016 cm-3) as the growth rate increases from 2 µm/hr to 5.2 µm/hr. In summary, systematic MOCVD GaN epitaxy and materials characterization were performed to investigate the effects of GaN growth rate on background impurities incorporation, charge compensation and charge transport properties in Si-doped GaN films. The increase of GaN growth rate leads to higher background C incorporation due to the use of higher TMGa precursor flow rate, as well as the reduction of electron mobility. This is identified as the key challenge to achieving high-quality thick GaN films with low controllable doping at low-mid 1015 cm-3. As a comparison, we will discuss the GaN film properties grown with CO2 laser excitation introduced during the MOCVD epitaxy. Acknowledgment: The authors acknowledge the funding support from Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy (DE-AR0001036), and U.S. Department of Energy's Office of Energy Efficiency and Renewable Energy (EERE) under the Advanced Manufacturing Office, FY18/FY19 Lab Call.

MOCVD GaN Epitaxy with Fast Growth Rates

Abstract Body: Metal-halide perovskite solar cells (PSCs) are the most promising photovoltaic (PV) technology owing to their cost-effective processing, tunable energy band-gaps, long carrier diffusion lengths, unique defect tolerance, and “self-healing” capabilities. Despite considerable efforts, the physical mechanisms for the inferior stability of PSCs are not well understood. Some researchers propose that structural defects are the main source of deterioration because they serve as a channel for moisture/oxygen stressors. Others claim that grain boundaries are benign, and the degradation is attributed to trapped charges in the perovskite absorber itself. A robust measurement approach that can characterize individual microstructures (e.g., grain, grain boundary, interface) is required. Focused ion beam (FIB) milling is a well-established sample preparation method that can remove the surface roughness of polycrystalline thin-films. An atomically-smooth surface allows local optoelectronic measurements of a microstructured PV with minimum artifacts from its innate rough surface. While extremely useful, high-energy ion beams (< 30 keV) irradiated on a hybrid organic-inorganic PSC may induce structural damage and/or chemical degradation. In this work, we investigate possible beam damage on PSCs prepared by focused argon (Ar) ion-beam at various doses. In addition, we use Monte-Carlo simulations to estimate the thickness of the damage layer. Our PSC devices were fabricated in a multilayer configuration: Au (60 nm) / Spiro-OMeTAD (220 nm) / MAPbI3 (550 nm) / MoOx (5 nm) / ITO (200 nm). Here, MA is methylammonium, and Spiro-OMeTAD stands for 2,2',7,7'-Tetrakis [N, N-di(4-methoxyphenyl) amino]-9,9'- spirobifluorene. We performed a series of Ar ion milling processes at room temperature (Fischione Model 1060), with the incident beam irradiated at shallow angles of 1° and 3°. The beam voltage was fixed at 4 kV, and the PSCs were milled for 5 min, 10 min, 15 min, and 20 min. At a first glance, we did not observe any notable changes with the samples milled at an incident beam angle of 1°. In contrast, the 3° milled PSCs showed color changes with an increase of milling time. We are currently working on quantitative EDS (Energy Dispersive X-Ray Spectroscopy) analysis to obtain the evolution of I/Pb ratio at different ion beam doses. It has been reported in the literature that the decrease of the I/Pb from 3 to a lower value indicates compositional deterioration (i.e., MAPbI3 is partially converted to PbI2). To gain a deep understanding into the interaction of the Ar ion beam with PSCs, we performed Monte-Carlo Simulations. In our model, 20,000 Ar ions at 4 keV were irradiated into MAPbI3 layer at a shallow angle of 3° and 30° from the surface. The estimated damage layer was calculated based on the substrate displacement density. Using a constant contour representing 5 % of the peak damage density, we obtained the damage depth of 8 nm and 13 nm for the incident Ar+ beam angle of and, respectively. The integrated analysis based on the simulations and the EDS measurements are in progress. Our results provide qualitative information of possible beam damage of PSCs that can occur during sample preparation. We will discuss the mitigation strategies to minimize the beam damage while characterizing the microstructural properties of PSCs. This work was supported by the U.S. Department of Energy’s Office of Energy Efficiency and Renewable Energy (EERE) under the DE-FOA-0002064 program award number DE-EE0008985. The assistance of Utah Nanofab is also acknowledged.

Impact of Ar Ion Beam Milling on Metal-Halide Perovskite Solar Cells

Abstract Body: Continued advancement in renewable energy science relies on the discovery of new organic photovoltaic materials with high quantum efficiency, stability, and reliability. Recently, non-fullerene acceptors (NFAs) have shown tremendous improvements in power conversion efficiency, ~18 %, that is attributed to wide spectral absorption, efficient exciton dissociation, and strong π-π interactions leading to excellent charge transport and collection. However, there still are significant losses in all steps of photoconversion that need to be understood and minimized. Conventional ultrafast spectroscopy methods have been effective in understanding intrinsic losses involving excited state relaxation and charge transfer in bulk heterojunctions. However, extrinsic losses are known to dominate in bulk heterojunctions due to non-ideal band energetics, disordered morphology and packing, and poor interfaces and contacts. Electric charge-based spectroscopies, such as impedance, transient, and noise spectroscopy, provide a direct probe to these relatively slow processes. Non-invasive in-situ characterization reveals performance-limiting dynamical processes in fully fabricated devices in operational conditions. In this talk, impedance spectroscopy methods will be discussed in the context of NFA-based organic solar cells. Emerging NFA-polymer systems, including perylenediimide-, indacenodithienothiophene-, and Y6-based NFAs, will be used to demonstrate the effectiveness of impedance spectroscopy methods in this context.1-5 In particular, the beneficial role of annealing in ITIC- and Y6-based blends will be elucidated through reduced bimolecular recombination that is further correlated with improved morphology and packing motifs. Integration of impedance parameters with intensity-dependent photocurrent enables more realistic device models that can distinguish the competing effects of end-group functionalization in NFA molecules. This method will be shown to reveal different routes of performance improvement via π-extension and fluorination of NFAs. In this manner, the new understanding gained in these systems is likely to pave the way for further optimization of high performance and stable solar cells. References: 1 Journal of the American Chemical Society 142, 14532 (2020). 2 Adv. Eng. Mater. 10, 2000635 (2020). 3 ACS Eng. Lett. 5, 1780 (2020). 4 ACS Appl. Mater. Inter. 11, 14166 (2019). 5 Adv. Funct. Mater. 27, 1703805 (2017).

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