Spain

Machine learning and high criticality applications

AEiC 2021 - 25th Ada-Europe International Conference on Reliable Software Technologies

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### Welcome Message from our Co-Chairs

Through this message, we want to give you our warmest welcome to the 25th Ada-Europe International Conference on Reliable Software Technologies (AEiC 2021). The special circumstances we all go through have made the conference a virtual event. Nonetheless, this will allow us to take advantage of the benefits of this format by using the Underline.io platform that allows remote participation of speakers and attendees and a virtual exhibition.
The platform will also provide a virtual space through Gather.Town to facilitate social interaction among participants, which, in addition to presenting state of the art research results, is one of the most important goals of a conference. This platform will hold various social events together with breaks and a poster session. 

The conference schedule includes a four-day program and exhibition from Monday to Thursday, with parallel tutorials on Monday, and keynotes, technical sessions and a Work-in-Progress session on the remaining three days. The technical sessions include the presentations of 13 journal-track papers, 5 industrial presentations and 6 invited talks on leading topics on reliable software technologies. The program will be completed with three outstanding keynotes that will delight the participants.

The main conference activities will be from 13:00 to 18:00 Central European Summer Time (CEST) to allow participants from America to Central Asia to attend to the conference sessions. Virtual social events are scheduled at the beginning and the end of each day. We encourage you to participate in these activities as well as visiting the exhibition. We look forward to meeting you virtually in June 2021!

**J. Javier Gutiérrez and Mario Aldea Rivas**
 // AEiC 2021 Program Co-Chairs

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technical paper

The current dependency of Artificial Intelligence (AI) systems on Cloud computing implies higher transmission latency and bandwidth consumption. Moreover, it challenges the real-time monitoring of physical objects, e.g., the Internet of Things (IoT). Edge systems bring computing closer to end devices and support time-sensitive applications. However, Edge systems struggle with state-of-the-art Deep Neural Networks (DNN) due to computational resource limitations. In this proposal, an introduced framework combines the Edge-Cloud architecture concept with BranchyNet advantages to support fault-tolerant and low-latency AI predictions. The implementation and evaluation of this framework allow assessing the benefits of running Distributed DNN (DDNN) in the Cloud-to-Things continuum. Compared to a Cloud-only deployment, the results obtained show an improvement of 45.34% in the response time. Furthermore, this proposal presents an extension for Kafka-ML that reduces rigidness over the Cloud-to-Things continuum managing and deploying DDNN.

A low-latency and fault-tolerant framework for distributed and deep neural networks over the cloud-to-things continuum

In space missions, boot software is in charge of the initialisation sequence of flight computers. The processor module in which it runs has a high tolerance to radiation, although not all devices have the same tolerance level. A boot software design capable of recovering from errors in the most vulnerable devices shall provide greater system reliability. This work has been carried out in the context of the boot software development for the control unit of the Energetic Particle Detector instrument on-board the Solar Orbiter mission. This mission operates close to the Sun where high-energy particles can cause single event effects on electronic devices, especially SDRAM and EEPROM, which show lower radiation tolerance than the other devices. This fact motivates this work, where a sensitivity analysis of the incidence of single event effects on the behaviour of the boot software is carried out. Specifically, a fault injection environment has been used to analyse the effect of “stuck-at” bits on the boot software ability to deploy and pass control to the application software. The results show the boot software vulnerability to this kind of permanent effects and have led to the implementation of a reliability-oriented design, presented in this paper.

Reliability-oriented design of on-board satellite boot software against single event effects

Everything we do at AdaCore is centered around helping developers build safe, secure and reliable software. Join us in this talk to learn about the comprehensive solutions we provide to build and maintain critical software investments.

Building and maintaining critical software investments

Safety Critical Multicore for Avionics Creating a multicore platform for safety critical avionics is the next major step for most avionics manufactures. While multicore processors are commonly used in most all other markets, the avionics industry has taken years to trust multicore technologies. This delayed acceptance is understandable due to an avionics system’s stringent safety and deterministic requirements which are not commonplace in many other industries. As a result, years of study have been invested to determine the challenges multicore processors pose for safety critical systems and then followed by the development of technologies and strategies that mitigate those challenges. Certification authorities and industry suppliers have invested in numerous studies and discussions over recent years to identify the issues multicore processors pose for safety critical systems. Formalized positions of these efforts are the FAA CAST-32A Positioning Paper, and EASA’s multicore certification review item (CRI). The crux of these papers (regarding software) focuses on bounding and controlling the interference patterns that exists when processor cores share resources. Unless interference patterns are addressed, real-time operations can be erratic and worse case execution (WCE) times can be longer than in a single core system. This paper will highlight the challenges of implementing multicore processors for any avionics developer. It will present Deos SafeMC and show how it helps address CAST-32A concerns. Specifically, the paper will introduce the means of which Deos SafeMC minimizes and bounds contention issues within multicore environments. For example, Deos cache partitioning and memory pooling features enable the user to configure the memory architecture to minimize cache thrashing. In addition, Deos provides the system architect the tools required to schedule applications across all cores in such a way that developers can coordinate applications such that they minimize conflicts over shared resources. While the paper uses Deos SafeMC an example of how one can address items brought up in CAST-32A, non-Deos users should also gain an insight into the concern multicore processors pose and to consider way in which they can be resolved.

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