United States

EM emanations during program execution contain important information about underlying system behavior creating a rich information-bearing side channel that can be used to profile software activity, detect code injections, and optimize software to minimize leakage. Yet there is currently a significant lack of tools for embedded software developers to analyze EM side-channel security of applications on an embedded processor. The only existing capability is based on cumbersome laboratory measurements, which require instrumentation expertise that a typical software engineer lacks, are expensive, provide limited observability, and are slow compared to what a computational tool flow enables. The goal of this project is to develop novel simulation-based approaches for characterization of EM fields emanated by software running on complex embedded processors.

In this poster, we present an overview of the current project status and results. As an initial step towards a tool for simulation-based analysis, we describe a hybrid empirical-simulation flow that uses near-field spatially-localized EM measurements to pre-characterize instruction EM fields and synthesize EM traces for full instruction sequences executed by a software program. In addition, we demonstrate our measurement-based setup and tracing flow for two applications on a 8051-based MCU: (1) evaluation of the vulnerability of the software against EM-based reverse engineering and disassembly of instructions executed by the MCU, and (2) evaluation of observability of program code modifications through out-of-band EM-based malware detection methods.

https://underline.io/speakers/44555-michael-orshansky


NSF Workshop on Micro/Nano Circuits and Systems Design

Simulation-based Analysis of EM Side Channels in Embedded Systems:From Software to Fields

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

You need to log in with the email address you registered with. Access credentials have been sent to your email. 

Please be sure to check your spam and other email folders if you do not see an email confirmation right away.

Please log in to explore this event.

It looks like you are not registered for this event. 

To access the site please register [**here**](https://www.irps.org/registration-fees). 

Please register!

IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


Non von-Neumann architectures such as in-memory computing (IMC) based on non-volatile memory devices have gained significant interest recently. In this project, we study a tiled, reconfigurable in-memory computing architecture, termed Memory Processing Unit (MPU) based on resistive random-access memory (RRAM) arrays. The tiled architecture allows practical neural networks to be mapped on IMC hardware using realistic RRAM arrays. Device and circuit non-idealities such as finite on/off, negative weight mapping, finite tile size, ADC quantization and device variations have been studies. A general design based on optimized IMC modules and a network-on-chip structure was developed and found to be able to effectively map different network models. The overall system performance has been analyzed and evaluated for different applications.

https://underline.io/speakers/59496-wei-lu



Memory Processing Unit (MPU) - An Efficient, Reconfigurable In-memory Computing Fabric

Energy-Efficient Deep Neural Network Design: From Time-based Circuits to Layer-wise Pruning

https://underline.io/speakers/59497-chris-kim

Energy-Efficient Deep Neural Network Design: From Time-based Circuits to Layer-wise Pruning

The Information Processing Factory (IPF) project aims to exploit self-awareness principles, together with lessons learned from
large-scale factories to contain complexity, achieve predictability and manage robust system design in the context of
autonomous Multi-Processor System-on-Chip (MPSoC) platforms in Cyber-Physical Systems (CPS) and the Internet of
Things (IoT). The goals of the project are to holistically couple key notions of self-awareness, self-organization, and large
scale factory automation to manage the multi-scale and multi-dimensional complexity of emerging MPSoC platforms that
execute dynamic workloads under a multitude of hard and soft constraints. Sensory information at multiple scales -- on-chip,
run-time systems, applications -- will need to be monitored, fused, and interpreted intelligently to assess health status,
mitigate adverse effects, and optimize system goals using a novel hierarchy of self-aware control loops that can both manage
complexity, as well as achieve guarantees. Additionally, the project aims to deploy a unique scalable distributed run-time
Major Activities:
verification (NUVA) architecture that should enable hardware-supported cross-layer monitoring of parametric specifications,
allowing both incorporation of trace-driven historical evidence for model building, as well as run-time execution for model
enhancement. The overall goals of the approach are to synergistically cover the multi-tiered abstraction hierarchy from low level
VLSI circuits to runtime OS and dynamic application software. The project will engage in a unique parallel collaboration
with DFG-funded German partners (at TU Braunschweig and TU Munich), with a dual focus on investigating self-aware IPF
principles for system-on-chip exemplars (US team), as well as for autonomous driving (German team). By leveraging the
German research partners' autonomous driving exemplar, the goal is to demonstrate self-aware IPF principles at multiple,
collaborative scales of autonomy and system design.

https://underline.io/speakers/6768-nikil-dutt

The Information Processing Factory – A Paradigm for Life Cycle Management of Dependable Systems

As Moore's law stalls, novel computing solutions are urgently needed to meet the ever-increasing computing demands from emerging applications such as modern machine learning tasks. With digital techniques running out of steam and emerging technologies pending material revolution, mixed-signal computing which combines circuit techniques in digital, analog, and time domains bring significant opportunities in the near future to dramatically improve computing efficiency.  The benefits of mixed-signal computing include high energy efficiency, compatibility with existing CMOS technology and EDA tools, and strong ties to physical world in a near-sensor or IoT environment.  In this poster, we will briefly discuss the concepts and examples of leveraging the dimensions of “time” in mixed-signal design to accelerate the computing tasks in emerging applications. 

https://underline.io/speakers/59498-jie-gu

Mixed-signal Computing for Emerging Applications

In-memory computing (IMC) SRAM has been demonstrated as a promising technique to significantly improve energy-efficiency for deep neural network (DNN) hardware accelerators. However, designing one involves setting many design variables such as the number of parallel rows to simultaneously activate, analog-to-digital converter (ADC) resolution at the periphery of a memory sub-array, precisions of various parts of a DNN model, etc., which affect energy-efficiency, accuracy, and area. Prior works have not investigated this multi-dimensional design optimization. To fill this knowledge gap, we present an SRAM-based IMC hardware modeling and optimization framework.

https://underline.io/speakers/60043-jae-sun-seo

SRAM-based In-Memory Computing for Energy-Efficient Deep Neural Networks

Bidirectional Brain Computer Interfaces play a key role in our effort to explore the human brain and hold the key to transformative changes in medicine and computing. however, significant barriers remain unaddressed by traditional, circuit-driven approaches. This research applies computational techniques to traditionally analog, mixed-signal and integrated power electronics to advance BBCI technology.

https://underline.io/speakers/59500-visvesh-sathe

Computationally Enhanced Bidirectional Brain Computer Interfaces

We discuss three key ideas for energy efficient nonvolatile memory and multistate nonvolatile synapses for neuromorphic computing :
1. Strain induced switching of magnetization in nanomagnets and MTJs.
2. VCMA control of topological state of magnetic skyrmions.
3. Strain control of domain wall position in nanoscale racetracks clocked by SOT.

https://underline.io/speakers/29802-jayasimha-atulasimha

Voltage control of nanoscale magnetism: For energy efficient memory and neuromorphic computing

This poster presents our work on rapid simulation and automated design of silicon photonics devices funded by the NSF under a CRII grant. Silicon Photonics is an exciting emerging technology platform which leverages existing CMOS Silicon-on-Insulator foundry infrastructure to guide and manipulate light on the nanoscale. Despite having great potential, silicon photonic devices are challenging to design and simulate due to the lack of analytical solutions, small wavelengths, and large structures involved. Simulations today rely on the Finite-Difference Time-Domain (FDTD) method. Unfortunately, FDTD suffers from slow convergence, poor accuracy, long simulation times, and significant numerical dispersion. The goals of this project are to couple a fast simulation method with optimization techniques to achieve rapid automated design of silicon photonics devices. To achieve this, we propose an alternative simulation approach which is based on boundary integral equations (BIE) in the frequency-domain. Our method is dispersion-free and only requires discretization of the material interfaces which reduces the number of unknowns significantly. The method is high-order accurate, achieving close to spectral accuracy, and only requires meshing at a few points per wavelength. Our poster introduces our BIE algorithms and implementations in both two and three dimensions and demonstrates recent results using our framework to rapidly simulate silicon photonic devices with high accuracy. We also demonstrate fast automated design of new, high-performance silicon photonic devices in both 2D and 3D by applying the adjoint method for computing the gradient of the objective function used for optimization. We have fabricated several of the devices optimized via our methodology and are currently in the process of measuring them to compare against our predicted simulation results. 

https://underline.io/speakers/59501-constantine-sideris




CRII: SHF: Ultra-fast Simulation and Automated Design of Silicon Photonics Devices

Associative Processing (AP) is a promising alternative to the Von Neumann model as it addresses the memory wall problem through its inherent in-memory computations. However, because of the countless design parameter choices, comparisons between implementations of two so radically different models are challenging for simulation-based methods. To tackle these challenges, we develop an alternative analytical approach based on a new concept called architecturally-determined complexity. Using this method, we asymptotically evaluate the runtime/storage/energy bounds of the two models, i.e., AP and Von Neumann. We further apply the method to gain more insights into the performance bottlenecks of traditional AP and develop a new machine model named Two Dimensional AP to address these limitations.

https://underline.io/speakers/59502-jing-li

CAREER: Associative In-Memory Graph Processing Paradigm: Towards Tera-TEPS Graph Traversal In a Box

With the advent of Internet-of-Things and the necessity to enable intelligence in embedded devices like mobile phones, smart watches etc., low-power and secure hardware implementation of neural networks is vital. Despite achieving super-human performance and classification accuracies on a variety of perception tasks, Deep Neural Networks (DNNs) have been shown to be adversarially vulnerable.  A DNN can be easily fooled into misclassifying an input with slight changes of pixel intensities. This vulnerability severely limits the deployment and potential safe-use of DNNs for real world applications such as self-driving cars, malware detection, healthcare monitoring systems etc. This poster investigates hardware aware optimization techniques to potentially resolve or resist software vulnerabilities (specifically, adversarial attacks). It aims to explore the design space of energy-accuracy-robustness trade-ff cohesively with algorithm-hardware co-design to create truly functional intelligent systems. This poster demonstrates robustness aware algorithms broadly applicable to the energy-efficient and secure implementation of DNN engines on both current complementary metal oxide semiconductor (CMOS) accelerator platforms and emerging memory technologies (with analog crossbar dot-product engines).

https://underline.io/speakers/59503-priyadarshini-panda

Downloads

Next from NSF Workshop on Micro/Nano Circuits and Systems Design

Memory Processing Unit (MPU) - An Efficient, Reconfigurable In-memory Computing Fabric

Similar lecture

Enhancing EM Reliability and Lifetime Modeling: A Multi-link Structure Approach