United States

Up-scaling of quantum information processors requires the cryogenic control CMOS devices to be operated in the few millivolt regime. However, MOSFETs show inverse subthreshold slope SS values which saturate well above the theoretical Boltzmann limit at cryogenic temperatures. In addition to this saturation of SS caused by band tailing, inflection degrades SS as a function of the gate voltage. We show gate stack engineering as an approach to counteract those phenomena which facilitate the realization of steep slope cryogenic MOSFETs.

DRC 2022

Interface Engineering for Steep Slope Cryogenic MOSFETs

steep-slope devices

gate-stack modifications

interlayer

band tailing

cryogenic mosfets

inflection

interface engineering

silicon nitride

**Welcome to ACL-IJCNLP 2021!**

The great event is jointly organized by the Association for Computational Linguistics (ACL) and Asian Federation of Natural Language Processing (AFNLP). 

As in previous years, the program of the conference includes a poster session, tutorials, workshops and demonstrations in addition to the main conference.


We were able to keep the registration fees similar to those charged for the virtual ACL 2020. The one fee allows attendance at the main conference and any/all tutorials and workshops. These fees would be $125 Regular Early and $175 Regular Late; $50 Student Early and $75 Student Late. Early registration closes at midnight July 11, 2021 (Eastern Daylight Time).

**Reminder:** It is ACL’s policy that at least one author of each accepted paper (including ACL Finding papers) must register for the conference.

**Reminder2:** Underline site will open closer to the event. If you already registered you will receive access detail

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IJCNLP-AACL 2021

The great event is jointly organized by the Association for Computational Linguistics (ACL) and Asian Federation of Natural Language Processing (AFNLP).

technical paper

[![](https://assets.underline.io/uploads/markdown_image/1/image/985c8a40b04e56675221c8549975de3c.png)](https://drive.google.com/file/d/1B70nPIeeeqdG4UU70NlYXuKVOHLRuJEo/view?usp=sharing)

### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

### **Topics**
* Biological Devices
* Devices for Extreme Conditions
* Heterogeneously Integrated Devices
* Memory Devices
* Modeling and Simulation of Devices
* Nanoscale and Vacuum Devices
* Optoelectronic and Optical Devices
* Other Emerging Devices
* Power Devices
* Quantum Devices
* RF and Terahertz Devices
* Spintronic and Magnetic Devices
* Thin-film Devices
* Wide-bandgap Devices
 
### **Invited Speakers**
* Patrick Fay, University of Notre Dame
* Susanne Hoffmann-Eifert, Peter Grünberg Institute
* Sanghyeon Kim, Korea Advanced Institute of Science and Technology
* Sriram Krishnamoorthy, University of California, Santa Barbara
* Mario Lanza, King Abdullah University of Science and Technology
* Xiuling Li, The University of Texas at Austin
* Marko Radosavljevic, Intel Corporation
* Siddharth Rajan, The Ohio State University
* Giordano Scappucci, Delft University of Technology
* Fisher Yu, University of Arkansas
* Wenjuan Zhu, University of Illinois at Urbana-Champaign




Registration is required to attend this event. If you have not already done so, please use the link below to register for a ticket to the conference:

https://www.mrs.org/drc-2022/registration

Registration Is Required

DRC continues to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an article in the Journal of the Electron Device Society. 
DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

We report in this work the GaN camel diode varactors which show good breakdown voltage, low reverse current density and good quality factor. This varactor technology combining has potential to be applied to RF front-ends where high power handling capability is imperative.

Free-Standing High Power GaN Multi-Fin Camel Diode Varactors

This work reports the first radio frequency (RF) characterization of ultra-thin ALD-grown amorphous indium oxide transistors down to 150 nm channel lengths. Record RF performance among amorphous oxide semiconductors is achieved including operation up to 22 GHz.

Record RF Performance of Ultra-thin Indium Oxide Transistors with Buried-gate Structure

We report for the first time that a single sub-nanosecond pulse can fully switch HfO2-based FeFET. We also study the polarization switching kinetics across 11 orders of magnitude in time and find an extremely steep time-voltage relation, which is captured by the domain nucleation model across this wide range of pulse widths

Sub-Nanosecond Switching of Si:HfO2 Ferroelectric Field-Effect Transistor

In this article, a novel FeFET with buried channel is proposed. Through TCAD simulations with the calibrated FE parameters, it is found that BC-FeFET opens up the path to eliminate ILD, leading to higher electric field in the FE layer and efficient polarization. An optimized BC-FeFET with ~3X higher memory window along with ~3X lower operating voltage range compared to the baseline FeFET is demonstrated. Moreover, as the channel is buried under a depletion layer, electron density at surface is reduced significantly during erase and read operation implying lower electron trapping/detrapping which can improve the endurance of the cell.

Buried-Channel Ferroelectric FET as Energy Efficient and Reliable 1T-NVM

Multilevel cell (MLC) Resistive Random Access Memory (RRAM) is an attractive technology option to realize ultra-high density, low-power memory arrays. Traditional 1-transistor 1-resistor (1T1R) bitcell suffers from adjacent state overlap due to the inherent RRAM variations which hinders the realization of MLC capability. In this work, we evaluate an alternate 2-transistor 1-resistor (2T1R) gain-cell RRAM bitcell topology that has higher read-out dynamic range and exhibits higher process variation tolerance compared to the baseline 1T1R bitcell.

Statistical Analysis of 2T1R Gain-Cell RRAM Bitcell for Area Efficient, High-Performance, and Reliable Multi-level Cell Operation

Movement of Current Filaments and its Impact on Avalanche Robustness in Vertical GaN P-N diode Under UIS stress

We present a simple composite analytical model that covers the entire electric-field range with excellent accuracy, with the use of an empirically-derived extrapolation function in the TFE-to-FE transition region. The composite TE-TFE-FE model successfully bridges the gap between TFE and FE regimes, allowing for accurate modeling of the Schottky barrier reverse current across the entire electric-field range. The closed-form and local nature of the composite model allows for easy implementation in TCAD tools for device design and analysis.

A Composite TE-TFE-FE Model for Schottky Barrier Reverse Current over the Entire Electric-Field Range

A versatile but extremely compact memristor model is introduced that is capable of emulating various memristive technologies while featuring fully analog, flux-linkage controlled operation as well as temporal tunability. Computation with time is a layer of complexity that could help break through barriers in the field of non-traditional compute and is extremely bio-mimetic, as the brain is exceptionally adept at temporal processing. This talk will explore some examples of temporal computation using simulated memristive hardware.

An Experimentally Validated, Universal Memristor Model Enabling Temporal Neuromorphic Computation

In this work, we demonstrate vertically stacked multilayer atomic-layer-deposited sub-1nm In2O3 field-effect transistors (FETs) with surrounding gate in a back-end-of-line (BEOL) compatible low-temperature fabrication process. Multilayer FETs with number of In2O3 layers up to 4 and 1.2 nm-thick HfO2 between each individual layer are fabricated. An enhancement of on-state current (ION) from 183 μA in single layer In2O3 FET to 339 μA in 4 layer device with on/off ratio of 3.4×10^4 is achieved.

Vertically Stacked Multilayer Atomic-Layer-Deposited Sub-1-Nanometer In2O3 Field-Effect Transistors with BEOL Compatibility

For p-type Cu2O thin film transistors (TFTs), high contact resistance is one of the critical issues that limit field effect mobility. Thus, to alleviate the contact resistance issue, in this work, we for the first time demonstrated Cu2O TFTs with nitrogen-doped Cu2O S/D interlayer. We observe a reduced contact resistance and improved field effect mobility when the N:Cu2O S/D interlayer is used.

Interface Engineering for Steep Slope Cryogenic MOSFETs

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