France

Recent advancements and applications in compact phased arrays, MIMO basestations and handsets, automotive radar, etc. are driving the need for RF power generation in CMOS technologies to accomodate high complexity systems that require RF output power. This presentation will provide an overview of CMOS device concepts up to architectural choices that have been proposed to improve RF power and efficiency in CMOS technologies. This discussion focuses on RF power amplifier concepts.

ESSCIRC ESSDERC Educational Events

Overview of RF Power Generation Using CMOS Technologies

rf cmos

power amplifiers

transmitters

#### Welcome to the 60th IEEE International Reliability Physics Symposium (IRPS)!

[![](https://assets.underline.io/uploads/markdown_image/1/image/f6b8cf9ecca2209dd3e0fcebe80a2915.png)](https://underline.io/events/282/reception) [![](https://assets.underline.io/uploads/markdown_image/1/image/e787ff477f8d2b687fb0b54d83d35e11.png)](https://drive.google.com/drive/folders/1GAycr7pPrZG2ZzZP-geUL8vGWswjCB1N?usp=sharing) [![](https://assets.underline.io/uploads/markdown_image/1/image/7492fafcc0c623afe96fe15207855ed9.png)](https://www.irps.org/)
 

**General Chair Welcome Message**

Welcome to IRPS 2022! When the IRPS Management Committee began making plans for Dallas, we recognized the strong desire by the reliability physics community to return to a face-to-face symposium that we last had in Monterey in 2019. But as time progressed, we recognized that travel restrictions were not being lifted as rapidly as we anticipated. Rather than leave out those of you who could not attend in person, we adopted a hybrid format allowing for both remote attendance and remote presentations. This is a first for IRPS and I am confident it will be a success for all.

With this new hybrid format, the symposium will return to the original five-day format with Tutorials and Year in Review on the first two days. The Technical Program, Keynote Talks, Workshops and Poster session will be held on the following three days. All of these (except Workshops and Posters) will be available via real-time streaming in the US Central Time zone with virtual attendees having Q&A access to the presenters. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees for a month after the symposium with the ability to communicate with the authors.

In 2020, we were planning on co-hosting the International ESD Workshop (IEW) ESD workshop when the COVID-19 pandemic hit. For 2022, IEW will be seamlessly embedded into the IRPS Program and will sponsor three tutorials, an invited talk, two technical sessions and two evening workshops focused on ESD and latch-up. And we continue our
collaboration with our sister conference, European Symposium on Reliability of Electron Devices Failure Physics and Analysis (ESREF) by hosting their Best Paper and the International Integrated Reliability Workshop (IIRW) by hosting their Best Student Paper.

Our primary objective is to maintain the symposium’s leadership role in the reliability physics of microelectronic devices by attracting leading researchers to present their work and providing attendees the best place to access this information. With all the buzz in the media about whether Moore’s Law has hit its limit, IRPS has been promoting expertise developed in silicon-based reliability over the past sixty years and expanding into new material areas. This year, eight of the technical sessions are devoted to reliability in topics outside of traditional silicon, including wide bandgap GaN/SiC, emerging memory and neuromorphic computing. I hope our ability to draw these communities together will accelerate the cross-fertilization of ideas. 

The Technical Program consists of four keynote speakers, twenty-three invited speakers and eighty-seven oral presentations organized in thirty technical sessions on eighteen reliability topics. Over two evenings, there will be ten Workshops and sixty-six Poster presentations that are designed to allow in person attendees and experts to interact
with one another. With eighteen tutorials covering topics ranging from fundamental transistor and memory reliability all the way up to automotive and complex system-level reliability, this year’s symposium provides an excellent learning opportunity for engineers and scientists new to reliability as well as experienced individuals wanting to explore new
areas. The Year in Review, which serves as a summary of research in the past year, will cover 3D packaging, emerging memory and aging aware circuit designs.

Finally, I would like to express my extreme gratitude to our patrons and exhibitors, whose support makes IRPS possible.
And to all of you, our in person and virtual attendees, for supporting this symposium for sixty years!

**Charles W. Slayman, General Chair** 
**of 2022 IRPS Management Committee**
 
**About IRPS**

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2022 Main Conference 

IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

For more than 50 years, Moore's Law has been driven by resolution improvements of lithography scanners which generate an image of the lithography mask on the semiconductor wafer. This image contains the patterning information needed to build up an integrated circuit.
The latest scanner generation uses 13.5 nm light at 0.33NA. Since the last 2 years they are now essential to produce leading edge semiconductor devices. To further increase the resolution ZEISS is working on next generation EUV optics. This optics consists of a highly flexible illumination system and projection optics with NA 0.55 enabling single-exposure sub 8nm half-pitch resolution to allow scaling beyond the next decade.
In this presentation we will explain the system design of the high-NA optical column and we will report on the manufacturing status of mirrors and frames. Furthermore, the buildup of the infrastructure including mirror polishing, coating, surface figure metrology, mirror handling, and integration tooling will be shown.

High NA EUV optics: preparing lithography for the next big step

Biological networks of neurons and synapses have the capacity to process multiple operations through short electrical pulses, also referred to as “spikes”, with very low energy consumption. Spiking Neural Networks (SNN) are a new form of Artificial Intelligence (AI) that aim to replicate these cognitive features in order to improve next generation computer’s performance. We present the design and simulation of an individual spiking laser to be used as a photonic neuron for a SNN scale-up. The neuron is a semiconductor laser optimized for pulsed operation through modification of the CEA Leti III-V on Si integrated continuous wave laser's heterostructure. A first demonstration of its neural features connected with synaptic functions is also reported.

Pulsed lasers neurons integrated on silicon for dense spiking neural network

LEDs for the UV-C spectral range gained increased attention in the recent years due to potential applications regarding the CoVID-19 pandemic. While its wide commercial uptake of UV-C LEDs is still inhibited by their relatively small efficiencies and lifetimes compared to conventional UV-light sources and compared to LEDs emitting in the visible spectral range, many improvements in the semiconductor device (LED chip and package) performance yield an accelerated entry into various markets.
The presentation will highlight the improvements enabling the achieved significant improvements in UV-C LEDs, such as crystalline quality of the chips, operation voltage, output power, lifetime and stability of their fabrication processes. 
The major application for UV-C LEDs is the large field of UV disinfection due to their UV-C radiation. Beyond this there are various other application fields. In the past years UV LEDs successfully entered other applications like streetlighting, horticulture lighting and general lighting. It always started as the underdog and a direct comparison with conventional sources was difficult and barely in the benefit of the new source. But again, the completely different properties of LED light sources are showing significant benefits in new system designs which have not been possible before.
Benefits of distinct UV-C LED sources and arrangements in different systems will be presented by explaining the features which enable the light source to be competitive and even perfectly suited for various disinfection applications.


Deep UV LEDs and its Applications

While digital synthesis has progressed enormously over the past decades, the synthesis of the analog and mixed-signal circuits has been lagging behind. Despite enormous progress in optimization methods for both analog circuit sizing and analog layout generation, adoption in daily industrial practice has been quite limited. Yet, the growing complexity of integrated systems to be designed today and the growing range of layout constraints introduced by advanced CMOS technologies at 16nm and below increase the need for efficient automated solutions. Also the verification of the designs becomes extremely challenging. Fortunately, novel algorithmic developments, including techniques from machine learning and artificial intelligence, provide the boost towards analog synthesis with increased functionality. Starting from an historical perspective, this presentation will sketch novel developments that aim to boost analog synthesis to the level desired in industrial practice.

Analog IC synthesis: the return of the Jedi

At ICCAD20, Tim from Google presented the paper titled "The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts" documenting roadblocks preventing fully open source ICs creation.

In less than a year the world has already rapidly changed thanks to Google releasing a fully open source, manufacturable 130nm PDK with open source tooling and no-cost MPW shuttle program! 

This talk will cover the success of Google investments in the open source IC space and the resulting huge explosion in open down to the transistor IC parts (including all of the RTL, tooling & PDK). It will also include exciting new annoucements and how new people can get involved.

Fully open source, manufacturable, PDK for 130nm process with fully open source tooling AND no-cost MPW shuttle program!

In order to truly unleash the productivity benefits offered by programmatic approaches to analog / custom circuit design, the analog designers themselves (as well as their managers) will need to not only be convinced that they should take this kind of approach, but in many cases, learn an entirely new set of skills, techniques, and approaches. In this talk, I will therefore offer perspectives gained through both industry and academia on how this seemingly obvious statement has and/or should drive the development/features of the frameworks/methodologies themselves, why I believe this drives us towards generator-based approaches as opposed to automation in the traditional sense, and some key next steps / objectives for the community.

Turning Analog Designers into Analog Generator Writers (and Users)

This presentation introduces a design methodology that is used by Infineon Technologies to automatically generate tape-out compliant analog circuits starting from the design requirements. The flow includes circuit sizing, layout and post-extraction verification, and can be applied to any process technology. We provide an example of its application to the generation of voltage regulators (VR), explain how the algorithms included in the flow handle various specification sets and showcase two different generated layouts.


ANAGEN: A Methodology for ANAlog Circuit GENeration

This talk presents a designer-friendly approach to produce custom layouts in advanced DRAM technologies. Memory system designs still rely on full-custom methodologies that manually produce circuit components and layouts for extreme performance optimization and area utilization, rather than exploiting automatic synthesis and place-and-route. However, as the device technology scales down, it becomes significantly challenging to produce custom layouts that meet all complicated design rule constraints. Therefore, an automated layout generation methodology is strongly required to enhance design productivity. While the automatically generated layouts from the methodology should meet all area and design constraints, the methodology should be organized to be readily adopted by circuit designers to utilize their expertise. In this talk, an automatic layout generation engine called layout with gridded objects (LAYGO) is presented, which produces DRC-clean layouts by combining handcrafted or PCell-based primitive templates and grid-based placement and routing functions. In this way, circuit designers can easily create their own layout generators with a minimum level of programming skills. A layout generation example in an advanced DRAM technology is presented, which produces >300 logic circuits instantly in a new technology node, which yields a >5x improvement in design productivity.

Applying automated design methodologies to advanced DRAM technologies

This talk describes a modular programmatic approach for design and verification of analog building blocks for utility circuits and Analog-to-digital converters. Use of programmatic design methodologies brings changes to organization of circuit design and verification. In this talk we describe practical aspects on how to take the programmatic methodology into use gradually in the organization. We demonstrate the use of Berkeley Analog Generator (BAG) for layout generation with vendor provided, already available device generators to reduce the configuration overhead, combined with modular design configuration to streamline re-use of the generators. Furthermore, we describe the verification methodology based on TheSyDeKick, a unified multi-mode modeling and verification environment that connects system models, digital RTL and analog circuit models in verification independently of whether they come from generators or more conventional design flows. We present the use of these methodologies in design of building blocks for time-based AD converters with circuit optimization examples.

Modular programmatic design and verification methodology for analog circuits in ADCs

5G and Beyond 5G applications are driving research towards highly integrated PA modules with multiband capabilities. Multiband requirements, along with the need for reduced power consumption, make the PA design highly critical since high PAPR signals require the PA to be backed-off from its peak power in order to achieve the necessary system linearity. This calls for an important shift from traditional PA design to more advanced PA architectures capable of handling signals with high PAPR while maintaining high efficiency and linearity on a broad frequency range. In addition, achieving high performance and reliability while maintaining compact size requires innovative thermal and electromagnetic management schemes. In this talk, I will give an overview of the challenges, recent progress and trends related to the integration of high efficiency PA design in RF-SOI technology for mobile applications operating below 6GHz.

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