France

Microelectronics plays a key role in fighting against global warming and preparing the world for the “post carbon age”. The performance of novel electronic based systems is constantly increasing by consuming less energy. This can be only achieved by novel systems that are designed in a holistic approach (Chip, passive components, package). The electronic package and interconnect solutions are contributing to these goals in a significant way. Besides this product focused potential for green electronics production and manufacturing of those is offering significant potential as well. Novel methods with respect to sustainable manufacturing have been achieved in this field and is contributing to reduce resource consumption in during production of electronic based systems of the future. These novel PCB and Packaging solutions as well as sustainable production concepts for them are under development in AT&amp;S under IPCEI Microelectronic Project and will be presented in this talk.

ESSCIRC ESSDERC Educational Events

PCB and packaging solutions for Green electronics

green electronics

substainabilitz

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines. AAAI-23 is the Thirty-Seventh AAAI Conference on Artificial Intelligence. The theme of this conference is to create collaborative bridges within and beyond AI. Like previous AAAI conferences, AAAI-23 will feature technical paper presentations, special tracks, invited speakers, workshops, tutorials, poster sessions, senior member presentations, competitions, and exhibit programs, and two new activities: a Bridge Program and a Lab Program. Many of these activities are tailored to the theme of bridges and all are selected according to the highest standards, with additional programs for students and young researchers. 
AAAI is providing you with a conference planner, which you can use to help organize your itinerary of activities. This includes talks to attend in person, talks to attend remotely, breaks with colleagues and your site seeing activities. To access this conference planner, please go to [https://aaai-2023.takemobi.io](https://aaai-2023.takemobi.io).

In order to access this site, you need to register. If you haven't already, please register [here](https://aaai.org/Conferences/AAAI-23/registration/).


AAAI 2023

The purpose of the AAAI conference series is to promote research in Artificial Intelligence (AI) and foster scientific exchange between researchers, practitioners, scientists, students, and engineers across the entirety of AI and its affiliated disciplines.

Microelectronics plays a key role in fighting against global warming and preparing the world for the “post carbon age”. The performance of novel electronic based systems is constantly increasing by consuming less energy. This can be only achieved by novel systems that are designed in a holistic approach (Chip, passive components, package). The electronic package and interconnect solutions are contributing to these goals in a significant way. Besides this product focused potential for green electronics production and manufacturing of those is offering significant potential as well. Novel methods with respect to sustainable manufacturing have been achieved in this field and is contributing to reduce resource consumption in during production of electronic based systems of the future. These novel PCB and Packaging solutions as well as sustainable production concepts for them are under development in AT&S under IPCEI Microelectronic Project and will be presented in this talk.

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This presentations deals with innovative approaches of 3D stacking Image sensors. Comparisons with conventionnal 3D vs sequential stacking is described.

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

The presentation is related to the EU-funded 3D-MUSE project where an extra layer of transistors is produced on top of a standard CMOS technology. Some readout circuits for radiation will be presented as well as how they can make use of several transistor layers. Examples are a multi-channel PMT, a thermal image sensor and a light radar. A simple TDC (Time to Digital Converter) will also be presented.

3D Integrated Circuits for Radiation Sensor Readout

In an industry wide consensus perpendicular spin-transfer-torque magnetic random-access memory (pSTT-MRAM) has matured to the memory of choice for replacing embedded FLASH solutions in the 2X nm technology nodes and beyond. However, especially this first entry point as a replacement for solder-reflow-capable eFLASH implies stringent requirements when it comes to high temperature data storage capabilities. In highly scaled pSTT-MRAM this demanding non-volatility can only be achieved by advanced free layer engineering. This energy barrier modulation needs to be carefully balanced in the boundary conditions of power consumption and endurance requirements. Sustaining and predicting this balance already at film-level or during patterning will be highly rewarding for the reliable manufacturing of this new technology. Here we present an early view on film-level and post-patterning magnetic metrology for embedded pSTT-MRAM.

Magnetic Metrology on Fully Integrated Embedded STT-MRAM

The architectural innovations of a new FPGA is presented.
The programmable Element, the routing structure and innovative switchboxes are explaned.

Novel Architecture for European FPGA

The modern world witnesses an ever-growing variety of consumer, home, automotive and industrial devices with network connectivity. 
Security is a crucial aspect in such systems and stakeholders will confirm that security constantly evolving. 
Therefore, NXP is very much involved in developing resilient, secure and trustworthy products that are a crucial building block for European data sovereignty. 
This results in the foundation that our customers use to build secure products.

In this presentation we will highlight the contributions of NXP Semiconductors Austria in the scope of IPCEI. 
This ranges from implementation security for high security products like Roots of Trust, 
over safe and secure battery management system for the green revolution as well as innovative 
application of technology for security use cases like Ultra-Wide-Band (UWB) radio for car access.

A connected world – Why security matters

5G standards effective deployment drives considerable technology challenges and implications on mobile devices design and requires innovative solutions to solve them. 
At the RF Front End Modules (FEM) level, the usage of new frequency bands, the complex use of the frequency bands (Carrier Aggregation, MIMO, QAM) and the coexistence with 4G networks are challenging the limits of existing acoustic filter technologies. 
A promising approach combining a thin single crystal LiTaO3 layer bonded on a Silicon substrate - so called Piezo On Insulator (POI) – together with the existing Surface Acoustic Wave (SAW) filter technology, enables to take advantage of guided waves that do not suffer from any radiation leakage. This SAW on POI approach will extend the use of the existing SAW technologies for higher performance integrated acoustic devices.
Triggered by the 5G filter market demand, the Smart CutTM technology has enabled high performance POI substrates supply chain in volume manufacturing, and paves the way to new design approaches for many applications beyond the Smartphone market.


Smart CutTM Piezo On Insulator (POI) substrates for high performance integrated acoustic devices

The IPCEI program at GF includes innovation along all technology readiness levels (TRLs). One example for very low TRL is the Reconficurable FET based on Schottky Barriers, close to 22FDX-processing. It enables camouflaging circuits for security applications, by e.g. providing NAND or NOR type cells, that can not be identified by reverse engineering. Another example is the development of a mmWave-variant of 22FDX allowing for operation frequencies typically in the 28-80 GHz regime, but also ranging up to 140 GHz. Characterisation of devices up to 3-4 times the operational frequency, a prerequisite for operation of the devices at these frequencies and showcases in the GHz regime for auto-Radar, 5 G and imaging radar are shown. These are just two examples, how the energy efficient 22FDX-technology at GF is enrichened by specialized variants and applications-specific- features.

Novel devices for security and showcases for mmwave with 22FDXTM

STMicroelectronics has developed a new generation of 40nm CMOS technology with embedded Non Volatile Memory targeted to support advanced Microcontrollers platforms. The presentation will briefly describe the very first implementation done with a standard Flash memory with high density but limited granularity (sector erase). We’ll then detail a second step, with a new NVM cell (eSTMTM) integrating a vertical select transistor to offer density similar to standard flash, but better erase control and granularity, that have been integrated in different IP blocks to suit MCU requirements. A latest step, will then be explained, showing further area reduction, as well as some perspective for generation ahead. From a circuit point of view, General Purpose MCUs done, with the initial technology, include a dual core for optimized performance and pass the 1000 DMips mark, while a derived version, using the optimized eSTMTM NVM cell, offer a 30% power consumption reduction. For secure MCU, 3 main applications have been targeted using the 40nm eSTMTM technology: circuit for contactless payment cards with biometry, harvesting enough energy to support a finger print sensor and verification, a circuit for embedded SIM with large NVM to allow high security loading and storage of virtual SIM cards and finally a combined embedded Secure Element and NFC controller (using the smallest eSTMTM cell) to support contactless applications in mobile phone such as payment, access control… Market for each applications represents hundreds of millions of circuits every year requiring robust, reliable and cost effective eNVM technologies.

Advanced Embedded Non-Volatile Memory solutions for General Purpose & Secure Microcontrollers

To address the increasingly challenging requirements of the RF front-end (RFFE) for 5G and also anticipated requirements for 6G, the 3D heterogeneous integration of GaN HEMT coupons on a RF-SOI technology is sought for combining the advantages of a high performance RF component and a capable Si based platform. Integration is performed at the transistor level rather than at a functional block level with conventional packaging methods. High performance RF passives, analogue, digital, and I/O functionality is performed by a 130nm RF-SOI technology with Cu and thick Cu metallurgy. GaN HEMT devices are instantiated as necessary to achieve design targets. Several examples of design innovation have been recently demonstrated by X-FAB including a 5.9-7.1GHz High-Linearity LNA, where the first stage cascode combines a HEMT and a Si NMOS exploiting higher output power and linearity of GaN. The second example is a SPST switch, where reduced insertion losses were observed in comparison to GaN on Si as a benefit of the integration method and also a significantly larger power handling capability than a Si counterpart. This discussion will include the present status and remarks on the future of this enabling technology.

multi-technology wafer level integration for RFFE applications

Both in Mobile and High-performance Computing (HPC) applications, efficient power supply of the processors was and is still being a big challenge for designers. Indeed, for these applications the power consumption is increasing while the power supply voltage is decreasing in alignment with the latest technological scaling. Thus, lowering and flattening the Power Distribution Network (PDN) impedance is more than ever important to mitigate the voltage fluctuation, the resonance and anti-resonance peaks caused by the PDN’s components. Such optimization is done by tuning the features of the different decoupling capacitors used along the power path from the power supply down to the processor. In this presentation, the benefits of using Low ESL silicon capacitors are demonstrated and compared to existing classical decoupling solutions. These components bring unprecedented design flexibility and significant improvements by reducing the voltage drop and enabling very low and flat PDN impedance.

Downloads

Next from ESSCIRC ESSDERC Educational Events

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

Similar lecture

FanoutNet: A Neuralized PCB Fanout Automation Method Using Deep Reinforcement Learning

.css-70qvj9{display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;}Downloads

Next from ESSCIRC ESSDERC Educational Events

Innovative Fine Pitch Architectures dedicated to Image Sensors: from Hybrid Bonding to 3D Sequential integration

Similar lecture

FanoutNet: A Neuralized PCB Fanout Automation Method Using Deep Reinforcement Learning

Downloads