France

When it comes to modelling materials of technological interest for microelectronics and their properties, the challenge is great, especially when considering current low-temperature processes, 3D architectures for the integration of ultra-thin, nanostructured materials with controlled performance. The continuum methods on which TCAD simulation in industrial environments typically relies are inherently unable to capture the resulting effects at these scales such as defect formation and growth mechanisms. 
In this talk, we will see how it has become necessary to implement a series of atomistic tools at different time and size scales to capture all the effects necessary for reliable process prediction. A review of atomistic methods will be proposed from the most conventional methods such as molecular dynamics and DFT to state-of-the-art methods such as going “beyond DFT” and Machine Learning potential. Examples on manufacturing process and defects characterization will be given.
Finally, one the main purpose of these studies is to help microelectronics engineers. Example of implementation of atomistic data into industrial TCAD tools will be given and discussed.

ESSCIRC ESSDERC Educational Events

What multi-level strategy for modelling processes and defects in semiconductors at the atomic scale? Current approaches, necessary developments and new needs.

multilevel modeling strategy

silicon

defects

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

technical paper

Future wireless standards require RF-sampling data converters to enable flexible multi-band operation over several GHz of instantaneous bandwidth. Efficient hardware organization in multi-antenna systems additionally requires co-integration of potentially many ADCs and DACs in a single chip with powerful data processing in the most advanced CMOS technologies. Besides the data converters, also a very high-quality clock generation, as well as calibration infrastructure must be integrated alongside the data converters. In this presentation we look at design examples of high-performance building blocks for such systems that have been implemented in one of the latest CMOS generations, with special emphasis on the digital assistance aspect in a DSP-heavy environment.

DSP-assisted RF-sampling data converters for 5G soft radio and beyond

The millimeter-wave (mmWave) and terahertz (THz) bands offer enormous bandwidth that is unparalleled, compared to the bandwidth available at lower microwave bands. This bandwidth has significant impact on the performance of wireless systems. The larger the channel bandwidth, the higher the throughput of wireless communication systems, and the higher the resolution of radar sensor systems. 
For the development of mmWave and THz wireless systems, advanced packaging platforms are required for system-integration of the ICs, antennas and other components required for system functionality. However, these platforms, also called antenna-in-package (AiP) platforms in published literature must meet some key requirements.
In this talk, the packaging requirements for mmWave and THz wireless applications are extensively discussed.


Packaging requirements for mmW & THz wireless applications

This talk will discuss the challenges to design and implement THz circuits in CMOS, as well as a discussion on applications. It will give an overview of the research results in this field by the MICAS group of KU Leuven, Belgium

THz circuits and applications

This presentation provides an overview of InP HBT integrated circuit technologies for mmWave and THz applications. Transistor and circuit performance will be reviewed with an emphasis on power amplifiers at mmWave and sub-THz frequencies. Heterogeneous integration techniques using wafer-scale 3D integration and device-scale microtransfer printing are also described.

InP technologies for mmW & THz wireless applications

The terahertz frequency range provides abundant bandwidth (25GHz ~ 50 GHz) to achieve ultra-high-speed wireless communication and enables data rates up to and above 100 Gbps. In this talk, I will present our early work on THz imaging and sensing with CMOS and SiGe HBTs. I will then present 6G wireless transceivers and discuss their performance and link impairments. I start with link budget considerations and address design trade-offs with respect to the used technology. The radio front-ends are manufactured in a SiGe BiCMOS 0.13um technology and operate at a tunable carrier of 220–260 GHz. The modules achieve data-rates from 20 to 100 Gbps with an EVM from 7% to 17% at a 1-meter distance using 16-QAM. I will further present our work on polarization diversity MIMO systems above 200 GHz. The MIMO link is established using a circular dual-polarization Tx and a dual-polarization Rx module. The polarization-diversity (left-handed circular polarization and right-handed circular polarization) is provided by a lens-coupled circularly polarized on-chip antenna. With this system, two independent data-streams of 55 Gb/s each were transmitted in parallel over a 1-meter line-of-sight distance, achieving an aggregated record data-rate of 110 Gbps.

SiGe HBT devices/circuits for mmW & THz wireless applications

Enabling the efficient processing of deep neural networks (DNNs) has becoming increasingly important to enable the deployment of DNNs on a wide range of platforms, for a wide range of applications. To address this need, there has been a significant amount of work in recent years on designing DNN accelerators and developing approaches for efficient DNN processing that spans the computer vision, machine learning, and hardware/systems architecture communities. Given the volume of work, it would not be feasible to cover them all in a single talk. Instead, this talk will focus on *how* to evaluate these different approaches, which include the design of DNN accelerators and DNN models. It will also highlight the key metrics that should be measured and compared and present tools that can assist in the evaluation.

How to Evaluate Efficient Deep Neural Network Approaches

As we march towards the age of “ubiquitous intelligence”, we note that AI and Machine learning are progressively moving from the Cloud to the Edge devices. The success of Edge-AI is pivoted on innovative circuits and hardware that can enable inference and limited learning, in hardware-constrained ultra-low-power (uW to mW) systems – an area of active research. In this talk, I will discuss the promises and outlook of Edge-AI and their applications in Autonomous Systems; and elaborate on some of our recent work on enabling such systems in sensor nodes and robotics. While some of these systems extend our understanding of statistical machine learning, a large class of circuits and systems are inspired by the information representation in the brain. I will talk about the design of such circuits and systems with an emphasis on the impact of mixed-signal circuits, near-memory and in-memory compute architectures, as well as algorithm-hardware co-design to realize the most energy-efficient Edge-AI ASICs for the next generation of smart and autonomous systems.

Neuro-inspired Edge-AI for Autonomous Systems

The explosive growth in the size of Artificial Intelligence (AI) models and the concomitant increase in compute intensity over the past few years is unsustainable without significant innovation across the stack. A non-von Neumann computational approach using in-memory compute is a paradigm shift that can deliver significant improvements in performance and energy efficiency for data-centric AI applications. Among the many memory options being evaluated, phase change memory (PCM) devices are attractive given their non-volatility, analog tunability & maturity of the technology. However, these devices also suffer from many non-idealities. This talk details innovations across materials, algorithms and architecture to address challenges posed by PCM device non-idealities to accelerate AI inference and training jobs.

Device, Architecture, and Algorithms Co-optimization for Scalable Analog Compute Technology

Computing-in-memory (CIM) is being widely explored to minimize powerconsumption in data movement and multiply-and-accumulate (MAC) for AI edge devices. In my talk, I will introduce several design techniques for CIM including both analog and digital approaches.

Basic introduction of SRAM based CIM including analog and digital approach

Artificial intelligence and deep neural networks (DNNs) have been successful across many practical applications, but state-of-the-art algorithms are compute-/memory-intensive. In-memory computing (IMC) has emerged as a promising technique to resolve the computation and memory access bottleneck. While many single-macro-level IMC prototypes have been demonstrated, integration and programmability challenges remain for system-level IMC accelerators. To that end, we present a programmable IMC accelerator (PIMCA) integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We will discuss architecture design and techniques employed for the PIMCA chip design, including a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of DNN layer types. The 28nm prototype chip achieves high system-level peak/average energy-efficiency of 437/289 TOPS/W.

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