France

Three key challenges in the design of modern closed-loop neurostimulators for the treatment of neurological disorders, such as intractable epilepsy, are discussed. The first challenge is the need for the best possible efficacy by implementing neuromodulation therapies that are custom-tailored for each patient. Here, the question of where to employ machine learning, whether within the medical device or remotely is addressed, with two energy-efficient implementation examples given: a long-effective-memory SVM and a spatiotemporal CNN. The second challenge is a clear patients’ preference for lower invasiveness – two methods are presented that enable selective recruitment of nerves by decomposing the stimulus signal as it is being delivered to the target. This allows to break the trade-off between invasiveness and selectivity, but requires complex stimulation waveforms applied concurrently with the neural activity recording. As a result, the third challenge is the need for tolerance to stimulation artifacts. Delta-sigma quantization techniques to track fast input transients, by adapting DAC step size, ADC reference voltage and ADC clock frequency, are presented to address this challenge.

ESSCIRC ESSDERC Educational Events

Artificially-intelligent Closed-loop Neurostimulators for the Treatment of Neurological Disorders

neuromodulation

neurostimulators

epilepsy

machine learning

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

The novel photo-acoustic CO2 sensor SCD4x launched by Sensirion in early 2021 represents a major innovation step in the miniaturization and cost-reduction of selective and long-term stable CO2 sensor technology. Being the first optical CO2 sensor compatible with surface-mounting technology and made for reflow soldering, the sensor allows for a broader adoption of indoor air quality monitoring both in residential air conditioning as well as internet of things devices. In my talk I will address how MEMS and CMOS technology combined with tailored assembly and packaging designs has enabled shrinking a measurement system previously reserved for scientific laboratories to an SMD component of the size smaller than a sugar cube.

Breaking the size barrier in CO2 sensing: the photo-acoustic CO2 sensor “SCD4x”

In recent years, an enormous surge of works is being carried out on developing new methods for magnetic devices for various kinds of healthcare applications. Miniaturising magnetic sensors offer the prospect to replace the bulky laboratory instruments with easy-to-use clinical platforms ranging from portable lab-on-a-chip diagnostics to wearable and implantable devices. It would bring down the cost, size and out-of-hospital use by several orders of magnitude. Implementation of such magnetic sensing microsystems using traditional CMOS technology is inefficient in terms of area, sensitivity and signal to noise ratio. Such inefficiencies have driven a significant effort to investigate the development of beyond-CMOS devices. Integration of magnetoresistive devices, e.g. Tunnelling Magnetoresistive (TMR), with CMOS technology provides an opportunity to produce and optimise powerful and low-power devices for low biomagnetic field applications. Such heterogeneously structure combining the CMOS circuitry interface and non-CMOS sensors higher performance electronics for detecting pico-Tesla magnetic field. 
The talk will introduce our research at the Microelectronics Lab (www.melabresearch.com) at the University of Glasgow on integrated electronic circuits and sensors with several different works addressing the development of architectures for the implementation of efficient biomedical wearable and implantable technologies. It presents findings and trends in magnetic sensing devices, including:
(i) Tunnelling magnetoresistive (TMR) sensors and circuit Interfaces for malaria parasite detection
(ii) Integrated micro–Nuclear Magnetic Resonance (micro-NMR) for point of care diagnostics
(iii) Implantable Magnetomyography (MMG) with magnetoelectric (ME) and TMR sensors 
(iv) Spintronic sensors based on Magnetic Tunnel Junction for wearable eye movements monitoring


Principles of Magnetic Sensing in Medical Microsystems

In less than a decade, optical sensing has become a key topic because of the growing potential in spectroscopy, chemical and biomolecular sensing, security and industry applications. This talk presents recent results on the chip level integration of the building blocks for chemical detection.

Challenges and Opportunities in the Miniaturization of the Optical Sensing

Photoplethysmography (PPG) is a non-invasive optical recording method to measure a number of vital signs in a very unobtrusive manner. While PPG has been employed in a clinical setting already for a few decades, it has regained popularity in the last decade specifically for wearable health applications. This talk will discuss the latest-state-of-the-art on ASIC readout architectures for low-power, high performance PPG readout circuits.

Photoplethysmography (PPG) readout interface circuit design techniques

Brain-machine interfaces (BMIS) of the future will be used to treat neurological disorders for which a cure does not exist yet. For this futuristic view to become a reality, we must overcome many technological challenges. A major goal is to increase the number of neurons that we can simultaneously interact with. To do so, future systems will record from more than a thousand channels at the same time. These systems will create a massive amount of raw data that needs to be compressed on the implant to lower the power consumption of the wireless link. As custom signal specifications for BMI applications become clearer and are diverging from those needed for basic neuroscience, there is an opportunity for application-specific lossy compression that improves further the power efficiency of these implants. In this workshop, we will cover the basic aspects of compression for BMIs and describe two different compression schemes for a motor BMI and an artificial retina.

Near-sensor compression in high-bandwidth brain-computer interface

To meet the prerequisites of monolithic indium phosphide based integrated terahertz (THz) technologies that are capable of achieving beyond-5G wireless communications system, a single computationally efficient circuit design tool is essential. Through the implementation of accurate and SPICE-compatible compact models and development of associated process design kits (PDK) for InP double heterojunction bipolar transistors (DHBTs), we demonstrate that next generations of cutting-edge high speed electronic systems will benefit from (i) dedicated parameter extraction procedure,(ii) validation of model parameter set against on-wafer high-frequency measurements and deembedding methods using dedicated test structures in the beyond 110 GHz range,(iii) extrapolation of key figures of merits to scaled device dimensions leveraging a scalable model card.

For the parameter extraction procedure, we investigate the bias, temperature, and frequency dependence of two III-V double heterojunction bipolar transistors technologies based on InGaAs/InP and GaAsSb/InP processes, using a HiCuM/L2 compact model-based multi-geometry scalable parameter extraction methodology. Very good agreement between the model simulations and experimental data is demonstrated. Transistor currents and junction capacitances show very good scaling, thereby allowing the separation of intrinsic and peripheral effects. 

Since thermal management is more critical in III-V technologies compared to Si-based ones, especially from the reliability point of view, for a more accurate description of electrothermal effects in InP HBTs, a new scalable model for the thermal impedance of III-V DHBTs that has been developed based on the physics of heat diffusion within the HBT architecture. The heat flow through both the emitter metal layers and toward the substrate are taken into account for the model development. The model constitutes of individual thermal contributions of the different regions of the intrinsic device and metal layers. On-wafer low-frequency S-parameters measurements have been performed on several device geometries to study the device dynamic self-heating. The model has been validated against the measurements showing good accuracy and scalability. Time-domain pulse measurements have also been performed to correlate with the frequency domain S-parameter measurements. Moreover, accuracy of the scalable model card has been validated against measurements up to 330 GHz on the InP DHBTs leveraging on-wafer measurements on passive devices (open/short) up to 500 GHz, achieved through TRL calibration and E-M simulation of designed test-structures. Finally, prediction of future III-V HBT technologies figures-of-merit for scaled device dimensions of a state-of-the-art InP DHBT is performed by using the generated scalable model card.

Compact Modeling and Parameter Extraction Strategies for InP Double Heterojunction Bipolar Transistors

The paper presents briefly the software used in the Ultimate projet for HiCuM/L2 compact model scalable parameter extraction. The video explains the software functionnalities and the basic theory beyond scalable physics based compact model parameter extraction. An example is given for junction capacitances with a demo of the software operation.

SMACH: a tool for bipolar model parameter extraction

In this presentation we discuss the design, implementation and measurements of Tb/s/channel optical communication circuits realized in III-V Lab InP DHBT process. Realizations using InGaAs- and GaAsSb-base devices will be presented and compared, from transistor to circuit performances.
The design flow is detailed with specific focus on key trade-offs to reach >3-4 Vpp output swings conjugated with >100 GHz analog bandwidth as well as circuits’ design for electro-optical systems with new transmission formats using innovative DSP algorithms allowing higher transmission rates and increased spectral efficiency, like m-ary pulse-amplitude modulation (m-PAM) or quadrature amplitude modulation (m-QAM) formats. We also present the design and measurements of digital multiplexing selector operation at record 212-GBd speed and its system implementation for intra data-center communications.


Recent advances in high-speed and large-swing integrated circuits implemented in InGaAs and GaAsSb InP DHBT for terabit-class optical communications

In this talk, power amplifier MMICs developed for emerging D-band (110-170 GHz) wireless communication links using InP DHBT technology will be presented. Power amplifiers designed for millimeter-wave frequencies in general suffer from low gain of the transistors and high loss in the interconnect structures. To complicate matters, it is foreseen that higher order modulation formats will be employed to enhance the spectral efficiency in future mm-wave wireless communication links and this dictates strict linearity requirements to the power amplifiers. 
The talk will describe circuit topologies able to exhaust the potential of the InP DHBT technology used and present a low-loss interconnect strategy suitable for the implementation of matching networks and power combining structures. The experimental results of implemented D-band power amplifier MMICs will be presented.

InP DHBT based Power Amplifiers for D-band (110 – 170 GHz) Wireless Communication Links

High data rate communications and high bandwidth communication and sensing systems demand for wideband MMIC operating over a bandwidth with excess of 100 GHz. This talk will introduce such MMICs and their design and characterization challenges. The talk will focus on the widest bandwidth and bandwidth limits as well as the achievable output power, noise figure and gain, as well as constant time delay versus frequency of operation. FBH has demonstrated > 150 GHz bandwidth with output power levels > 12 dBm and concurrent noise-figures of < 9 dB, which allow for robust wideband receive modules and high power transmit modules. Results will also be shown on signal switches and preliminary results on wideband mixers. Routes towards even large bandwidths will be discussed and improvement in output power will be outlined.

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