Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9172.pdf

**Abstract:**

This paper presents a real-time output 50-GS/s 8-bit time-interleaved (TI) analog-to-digital converter (ADC) with dedicated calibration techniques and deterministic latency, where the full-speed converted data are output by 16-lanes transmitters. gain, offset and time-skew calibration optimize the ADC\&#39;s performance. Fabricated in a 40-nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.80 dB at 50 GS/s with a 19.123-GHz input. respectively. The ADC core occupies an area of 1.232 mm2 and consumes 894 mW.

ESSCIRC ESSDERC 2021

A Real-Time Output 50-GS/s 8-Bit TI-ADC with Dedicated Calibration Techniques and Deterministic Latency

fractional delay filter.

deterministic latency

time-interleaving

analog-to-digital converter (adc)

transmitter

calibration

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9172.pdf

**Abstract:**

This paper presents a real-time output 50-GS/s 8-bit time-interleaved (TI) analog-to-digital converter (ADC) with dedicated calibration techniques and deterministic latency, where the full-speed converted data are output by 16-lanes transmitters. gain, offset and time-skew calibration optimize the ADC\'s performance. Fabricated in a 40-nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.80 dB at 50 GS/s with a 19.123-GHz input. respectively. The ADC core occupies an area of 1.232 mm2 and consumes 894 mW.

technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9098.pdf

**Abstract:**

In this paper, a quadrature error corrector (QEC) for next generation DRAM interface is proposed. The proposed QEC corrects duty-cycle error and 4-phase skew simultaneously for high speed operation in DRAMs. The internally used half rate two-phase clocking reduces power by 35% and area by 40%, respectively. A prototype chip achieves less than 1.84˚ phase error for a 12.8 Gb/s and has a correctable range 100.5˚ within 120 ns lock-time using successive approximation register (SAR). A re-lock scheme to cope with voltage and temperature variation during chip operation is also proposed. It occupies an active area of 0.01 mm2 while consuming 9.8 mW with 1.0-V supply.

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9204657

**Abstract:**

In this work, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film siliconon-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: the Effect of Back Bias on Drain Current and Transconductance

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9201379

**Abstract:**

This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning is found to be temperature independent, allowing extra drain current improvement. This is particularly interesting for short channel devices, whose drain current gain with temperature lowering is expected to be smaller in comparison with long channel MOSFETs. LFN is characterized by means of time-domain current sampling measurements. Moderate and strong inversion regimes are investigated. The carrier number with correlated mobility fluctuations model can well describe the 1/f noise behavior down to 4.2 K. The physical origin behind the drain current noise-to-signal power augmentation with temperature lowering could be mainly attributed to the normalized transconductance improvement.

Performance and Low-Frequency Noise of 22-nm FDSOI Down to 4.2 K for Cryogenic Applications

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9170592

**Abstract:**

We present a digital cell library optimized for 4.2 K to create controllers that keep quantum processors coherent and entangled. The library, implemented on a standard 40nm-CMOS technology, was employed in the creation of the first 4.2 K RISC-V processor. It has achieved a minimum supply voltage of 590mV, energy-delay product of 37fJ/MHz, and maximum operating frequency of 740MHz, all at 4.2 K in continuous operation. These results have been obtained from stand-alone characterization, successfully executing small C programs/benchmarks at 4.2 K. The overall performance of the library compares well against state- of-the-art libraries designed for room temperature. In particular, we compared the performance of the proposed library against a foundry supplied library for the same process in several combinational benchmark circuits, showing significant improvements in power dissipation and frequency of operation.

A Cryo-CMOS Digital Cell Library for Quantum Computing Applications

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9146534

**Abstract:**

A scalable eight channel DAC designed in a TSMC 65-nm CMOS technology for generation of solid-state quantum bit (qubit) bias voltages is presented. Measurement results of the DAC and some additional auxiliary components like an on-chip amplifier and sigma-delta modulator at 6 K are discussed. With a low-power consumption of 2.7 μW per channel, the DAC fulfills the requirements to be placed next to qubits inside a mixing chamber of a dilution refrigerator, showing a promising way for scaling qubit numbers toward a quantum computer.

Bias Voltage DAC Operating at Cryogenic Temperatures for Solid-State Qubit Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9270.pdf

**Abstract:**

The paper presents a low-power transmitter (TX) as a part of a fully-integrated 57-66 GHz FMCW radar system. The TX path includes a BPSK modulator and it is optimized for short-range operation with 0 dBm output power. A band-tuning technique is used for covering the 9 GHz band and it is tuned as the LO frequency is swept. The LO distribution is designed in a modular approach to be able to extend the number of TX paths for MIMO operation. Integrated in GF 22-nm FDSOI CMOS technology, each TX path is 570x100 um2 and consumes 17 mW.

An Optimized Low-Power Band-Tuning TX for Short-Range FMCW Radar in 22-nm FDSOI CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9116.pdf

**Abstract:**

A 139.5-157.7 GHz D-band I/Q radar receiver with an on-chip antenna and a spillover resilient N-path baseband filter is presented. Spillover and its manifestation based on the chirp rate is discussed and a filter for spillover mitigation is implemented. The radar is characterized with 55 dB conversion gain, 8dB NF (5.6 dB EINF) and 26dB narrow-band spillover attenuation. The receiver is also capable of selectively mitigating very close-by large reflectors and the system power consumption is 67mW.

A 67mW D-Band FMCW I/Q Radar Receiver with an N-Path Spillover Notch Filter in 28nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9059.pdf

**Abstract:**

This paper presents a transmitter(TX) and an adaptive receiver(RX) for the next-generation automotive camera link with PAM-4 signaling. TX utilizes push-pull current drivers and 3-tap FFE to improve impedance matching and eye margin, respectively. To cancel the sampler offset for a lower BER, instead of adjusting data and threshold levels(dtLevs), the gain of a programmable gain amplifier is adjusted adaptively under fixed dtLevs. The TX delivers 8-Gb/s PAM-4 signal to the adaptive RX through a 12-m cable(22-dB loss) with a BER of 1E-8. The prototype chips consume 65.2 mW(excluding PLL), exhibiting an FoM of 0.37 pJ/bit/dB.

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9062.pdf

**Abstract:**

This work presents a dielectric waveguide communication link at 135 GHz, reaching 27 Gb/s non-return to-zero (NRZ) communication without any equalization at a bit-error-rate (BER) below 10-12 and up to 50 Gb/s 4-level pulse-amplitude modulation (PAM4) over 3 m of fiber at a BER below 10-6 when equalization is applied. This work is the first to break the 25 Gb/s barrier at distances of 1 m and above. These results are achieved by combining a low power, multilevel mm-wave transceiver with a coupler on printed circuit board (PCB) and a fiber design optimized for low dispersion.

A PAM4 Dielectric Waveguide Link in 28 nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9253.pdf

**Abstract:**

A 55nm SiGe BiCMOS ADC front-end is reported with record 200-GS/s sampling rate and SNDR larger than 32 dB and 25.3 dB up to 45 GHz and 63 GHz, respectively. This performance is enabled by the architecture of the front-end with a single level of samplers which maximizes bandwidth and linearity, by the reduced-voltage MOS CML switch, and by a dc-to-62 GHz, 25%duty-cycle non-overlapping quadrature clock generator. The total power consumption of the ADC front-end is 635 mW.

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