Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9260.pdf

**Abstract:**

This paper presents reliability assessment of basic integrated circuits designed for analog and RF applications based on extensive circuit simulations using the aging compact model, HiCuM-AL v3.0, dedicated to SiGe HBTs. The physic-based aging compact model implemented within HiCuM model is based on trap generation-annihilation mechanisms as well as the Fick hydrogen diffusion law. The model has been validated against results from HBT aging tests under various stress conditions followed by aging model parameter extraction. Due to its extensive use in integrated circuit blocks, different current mirror configurations subjected to mixed-mode stress conditions are studied and analyzed in order to quantify the impact of HC degradation on individual HBTs as well as on overall circuit performances.

ESSCIRC ESSDERC 2021

Impact of Hot Carrier Degradation on the Performances of Current Mirrors Based on a 55 nm BiCMOS Integrated Circuit Technology

current mirrors

circuit aging

aging compact model

sige hbt

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9134399

**Abstract:**

This paper describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-interleaved ADC (TI-ADC), clock generation, clock distribution, feed-forward equalizer (FFE), decision feedback equalizer (DFE), and calibration. The TI-ADC is implemented as a 56–67-GSa/s, 36-way arrangement of dualcomparator SAR ADCs (SAR subADCs). The Rx achieves BER better than 1e-4 for a data rate as high as 127 Gb/s, with 3.2e-4 BER at 134.4 Gb/s, over a 15-dB die-to-die loss channel and achieves 3e-6 BER over a 33-dB die-to-die channel loss at 28-GHz Nyquist while consuming 5.1 pJ/b of power, excluding DSP power.

A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9131847

**Abstract:**

This letter presents the analysis of phase noise generated from the base resistance in the bipolar transistor Class-C oscillator. It is found that the efficient pulsed current of transistors enhances this noise contribution. Moreover, the impact of the base resistance noise rises quickly with the oscillation amplitude, limiting the benefits of rising the supply voltage to reduce phase noise and penalizing the Figure of Merit (FoM). Furthermore, the amplitude stability problem is addressed and a simple expression for the maximum tail capacitance to prevent instability is derived. The phase noise analysis is validated by the measurements on a 12-GHz Class-C HBT VCO. With 3.4-V supply, the VCO reaches −187-dBc/Hz FoM, limited by the base resistance noise. The impact of this noise source is reduced by decreasing the supply voltage, and with 1.8-V supply, the VCO maintains a state-of-the-art phase

Impact of the Base Resistance Noise and Design of a −190-dBc/Hz FoM Bipolar Class-C VCO

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9131827

**Abstract:**

This paper presents a 14-GHz digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change in one sample of a 200-MHz clock. The architecture is based on a fractional-N bang-bang digital PLL exploiting an adaptive DCO-tuning requantizer, which mitigates the segmentation-induced nonlinearity of the DCO, and a novel deskewing circuit, which improves the EVM at high bit rates. The modulation error, expressed in terms of RMS value of the EVM, is below -42 dB for a 250-Mb/s 32-PSK modulated carrier. The phase modulator, integrated in a 28-nm CMOS process, consumes 31.5-mW power, achieving 0.13-nJ/bit energy consumption.

A 250-Mb/S Direct Phase Modulator with -42.4-dB EVM Based on a 14-GHz Digital PLL

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9158387

**Abstract:**

This paper presents a 24-MHz ultralow-power and low-phase-noise complementary Colpitts crystal oscillator. Class-C operation is realized by biasing the oscillator always in the weak-inversion region with the proposed circuit. A Langasite-type CTGS (Ca3TaGa3Si2O14) crystal resonator, with the characteristics different from those of quartz (SiO2), helps to reduce the startup time. An injected-gm-booster is implemented to speed up the oscillation further. Prototype chips in 65-nm CMOS were evaluated with CTGS and quartz resonators. With each type, the lowest steady-state power consumption, and the best jitter FoM have been achieved. With the CTGS resonator, the startup energy as low as 10 nJ has also been achieved.

Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171855

**Abstract:**

In this letter, a low cost, compact, and systematic method for generating a short pulse and efficiently delivering it to low impedance loads is proposed. The load can be a resistive on-chip or off-chip load, an antenna, or another stage such as a power combiner. The technique is inspired by time-domain reflectometry from a short-circuited termination. The technique is fully compatible with the CMOS technology. To show the feasibility of the idea, two chips are fabricated and tested in a low cost 0.11-μm CMOS process with fT ≈ 80GHz. The full-width at half maximum (FWHM) of the pulses are 6.8 ps and 8.8 ps, and the amplitudes over a 50 load are 0.62 V and 1 V. Either of the chips occupies 1160 × 540μm2 in area.

Reflection-Based Short Pulse Generation in CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205911

**Abstract:**

A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gb/s ultrawideband transceiver fabricated in 28-nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops, one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing is used to control a back-bias-controlled oscillator and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature variations, including skewed process corners. The CR occupies a silicon area of 0.043 mm², locks in less than 1.1 μs, generates an RMS long-term jitter of 6.5 ps, and consumes 1.034 mW while in-lock. This results in an energy value of 0.414 pJ/cycle and a jitter FoM of −224 dB.

A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9255.pdf

**Abstract:**

Silicon and its native oxide SiO 2 are the most commonly used materials in semiconductor device technology. After decades of research in this field, details of the initial oxidation and the subsequent O migration and amorphization are still a subject of interest. In this paper, we present a multiscale modeling approach to investigate the oxidation process of a Si(100) surface. Starting from the adsorption and dissociation of single O 2 molecules, we further extended our investigations towards the initial oxidation of the first Si layer and subse- quent O migration. Finally, we construct a realistic model of a Si/SiO 2 interface consisting of around 5000 atoms. The employed simulation techniques used in this study range from density functional theory (DFT) to density functional based tight binding (DFTB) to classical molecular dynamics (MD).

Multiscale Modeling Study of Native Oxide Growth on a Si(100) Surface

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9152.pdf

**Abstract:**

A ML based framework is presented to predict the formation and structure of defect in amorphous structures, aiming at reducing the computational costs which these studies require. The framework is applied to the prediction of hydroxyl E\' center defects in amorphous silicon dioxide. The results demonstrate a competitive level of accuracy, while being computationally inexpensive, when compared to DFT.

Machine Learning Prediction of Defect Structures in Amorphous Silicon Dioxide

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9266.pdf

**Abstract:**

It is well established that oxide defects are a major threat concerning the reliability of electronic devices. Point defects like the oxygen vacancy and hydrogen related defects like the hydrogen bridge and the hydroxyl-E\' center can trap charges from the Si substrate during operation. Here we present a statistical study of parameters by analyzing 144 defects of each type in amorphous SiO2 . We use density functional theory in conjunction with a hybrid functional to provide a large and accurate dataset of defect parameters such as the relaxation energy or the charge transition level and link them to bias temperature instability in nMOSFET devices.

Statistical Ab Initio Analysis of Electron Trapping Oxide Defects in the Si/SiO2 Network

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9264.pdf

**Abstract:**

This work presents a new method of noise model implementation for circuit simulations, which enables the generation of Lorentzian-type spectra. The importance of Lorentzian noise modeling is explored in contrast to classic 1/f or Random Telegraph Noise (RTN) modeling, in terms of PSD, total noise power, and device-to-device noise variability reproduction, through analysis of experimental data. The Verilog-A modeling methods for both types of Lorentzian noise are demonstrated and validated, using a Lambert-W function charge-based drain current model. Finally, fundamental digital and analog circuits such as the Ring Oscillator are used to showcase the usefulness and applicability of the “VERILOR” model in circuit noise simulations.

Downloads

Next from ESSCIRC ESSDERC 2021

A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

Similar lecture

Monte Carlo Comparison of n-Type and p-Type Nanosheets with FinFETs: Effect of the Number of Sheets

.css-70qvj9{display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;}Downloads

Next from ESSCIRC ESSDERC 2021

A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

Similar lecture

Monte Carlo Comparison of n-Type and p-Type Nanosheets with FinFETs: Effect of the Number of Sheets

Downloads