Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9255.pdf

**Abstract:**

Silicon and its native oxide SiO 2 are the most commonly used materials in semiconductor device technology. After decades of research in this field, details of the initial oxidation and the subsequent O migration and amorphization are still a subject of interest. In this paper, we present a multiscale modeling approach to investigate the oxidation process of a Si(100) surface. Starting from the adsorption and dissociation of single O 2 molecules, we further extended our investigations towards the initial oxidation of the first Si layer and subse- quent O migration. Finally, we construct a realistic model of a Si/SiO 2 interface consisting of around 5000 atoms. The employed simulation techniques used in this study range from density functional theory (DFT) to density functional based tight binding (DFTB) to classical molecular dynamics (MD).

ESSCIRC ESSDERC 2021

Multiscale Modeling Study of Native Oxide Growth on a Si(100) Surface

dftb

silicon

sio2

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9169677

**Abstract:**

This letter presents a wireless transmitter (TX) front end in which the functionalities of digital-to-analog conversion, baseband filtering, and signal upconversion are implemented by a passive switched-capacitor (PSC) network. The result is a versatile architecture that fully benefits from CMOS scaling. The front end was integrated in a 65-nm CMOS technology and can support various channel bandwidths simply by adjusting the switching frequency for the PSC network. Thanks to its third-order reconfigurable filter, it maintains a thermal noise floor better than -156 dBc/Hz at a power dissipation of 45 mW. The measured prototype achieves an ACLR2 of -57 dB and an EVM of -31 dB for a 20-MHz 64-QAM OFDM and a 20-MHz 16-QAM signal, respectively.

A Reconfigurable Passive Switched-Capacitor TX RF Front End with −57 dB ACLR2

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9152038

**Abstract:**

True-time-delays enable wideband analog and hybrid beamforming by mitigating the beam squint problem. This paper reports a true-time-delay beamforming receiver supporting delays up to three carrier-frequency cycles. The inherent delay scaling with frequency enables true-time-delays for large arrays at low-GHz frequencies where long delays are required due to lambda/2 antenna spacing. The delays are implemented through delayed resampling of a passive mixer\'s discrete-time output. Driving the mixers with pulse-skipped local oscillator (LO) signals allows the delay range to exceed one carrier cycle.A polyphase receiver structure prevents aliasing of noise and unwanted tones caused by LO pulse-skipping.

A 0.6–4.0 GHz RF-Resampling Beamforming Receiver with Frequency-Scaling True-Time-Delays Up to Three Carrier Cycles

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9144258

**Abstract:**

A TX power calibration loop with high accuracy for millimeter-Wave (mm-Wave) automotive radar application is presented. The loop consists of a calibration logic, a variable gain amplifier (VGA), a power amplifier, a power detector, an analogue-to-digital convertor (ADC) and a temperature sensor fabricated in a 40 nm CMOS process. The digital power calibration loop is implemented to adjust the monitored detector output voltage to a predetermined target voltage according to a temperature by controlling the gain of the VGA. To achieve high power accuracy and stability against temperature variation, the proposed power detector is designed to realize flat or monotonic characteristics against temperatures by optimizing a second distortion. Measured calibrated output power shows 10 dBm ±0.5 dB over wide temperatures ranging from −20˚C to 125˚C.

Power Calibration Loop with High Accuracy of 10 dBm ±0.5 dB for a 77-GHz Radar Application

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9187850

**Abstract:**

A 280-GHz, fully integrated and digitally controlled multiport coherent radiator is presented. The silicon die acts as a chip-scale dielectric resonator antenna (CSDRA) and is excited by four differential loop inductors. The chip incorporates a balun for an X-band input signal, a 1-4 ultracompact differential Wilkinson splitter, and four ×27 active multipliers chain (AMC), which drive the four exciting elements. Highresolution, digitally controlled true time delay (TTD) elements, based on digitally controlled artificial dielectric transmission lines (DiCAD), are used to calibrate the variations between channels to optimize overall broadside radiated power and enable beam steering of ±15°. High-resolution DACs are used to accurately set the bias through a 3-wire SPI module. Fabricated in 65-nm CMOS, the 1.4×2-mm 2 chip achieves a record EIRP of +21 dBm, a TRP of +8.5 dBm, and a power density of 2.25 mW/mm 2 with 0.72% total efficiency, without using any external lens, superstrate, or postprocessing.

A 280-GHz Digitally Controlled Four Port Chip-Scale Dielectric Resonator Antenna Transmitter with DiCAD True Time Delay

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9134399

**Abstract:**

This paper describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-interleaved ADC (TI-ADC), clock generation, clock distribution, feed-forward equalizer (FFE), decision feedback equalizer (DFE), and calibration. The TI-ADC is implemented as a 56–67-GSa/s, 36-way arrangement of dualcomparator SAR ADCs (SAR subADCs). The Rx achieves BER better than 1e-4 for a data rate as high as 127 Gb/s, with 3.2e-4 BER at 134.4 Gb/s, over a 15-dB die-to-die loss channel and achieves 3e-6 BER over a 33-dB die-to-die channel loss at 28-GHz Nyquist while consuming 5.1 pJ/b of power, excluding DSP power.

A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9131847

**Abstract:**

This letter presents the analysis of phase noise generated from the base resistance in the bipolar transistor Class-C oscillator. It is found that the efficient pulsed current of transistors enhances this noise contribution. Moreover, the impact of the base resistance noise rises quickly with the oscillation amplitude, limiting the benefits of rising the supply voltage to reduce phase noise and penalizing the Figure of Merit (FoM). Furthermore, the amplitude stability problem is addressed and a simple expression for the maximum tail capacitance to prevent instability is derived. The phase noise analysis is validated by the measurements on a 12-GHz Class-C HBT VCO. With 3.4-V supply, the VCO reaches −187-dBc/Hz FoM, limited by the base resistance noise. The impact of this noise source is reduced by decreasing the supply voltage, and with 1.8-V supply, the VCO maintains a state-of-the-art phase

Impact of the Base Resistance Noise and Design of a −190-dBc/Hz FoM Bipolar Class-C VCO

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9131827

**Abstract:**

This paper presents a 14-GHz digital-intensive phase modulator circuit, which is able to enforce an arbitrary carrier phase change in one sample of a 200-MHz clock. The architecture is based on a fractional-N bang-bang digital PLL exploiting an adaptive DCO-tuning requantizer, which mitigates the segmentation-induced nonlinearity of the DCO, and a novel deskewing circuit, which improves the EVM at high bit rates. The modulation error, expressed in terms of RMS value of the EVM, is below -42 dB for a 250-Mb/s 32-PSK modulated carrier. The phase modulator, integrated in a 28-nm CMOS process, consumes 31.5-mW power, achieving 0.13-nJ/bit energy consumption.

A 250-Mb/S Direct Phase Modulator with -42.4-dB EVM Based on a 14-GHz Digital PLL

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9158387

**Abstract:**

This paper presents a 24-MHz ultralow-power and low-phase-noise complementary Colpitts crystal oscillator. Class-C operation is realized by biasing the oscillator always in the weak-inversion region with the proposed circuit. A Langasite-type CTGS (Ca3TaGa3Si2O14) crystal resonator, with the characteristics different from those of quartz (SiO2), helps to reduce the startup time. An injected-gm-booster is implemented to speed up the oscillation further. Prototype chips in 65-nm CMOS were evaluated with CTGS and quartz resonators. With each type, the lowest steady-state power consumption, and the best jitter FoM have been achieved. With the CTGS resonator, the startup energy as low as 10 nJ has also been achieved.

Ultralow-Power Class-C Complementary Colpitts Crystal Oscillator

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171855

**Abstract:**

In this letter, a low cost, compact, and systematic method for generating a short pulse and efficiently delivering it to low impedance loads is proposed. The load can be a resistive on-chip or off-chip load, an antenna, or another stage such as a power combiner. The technique is inspired by time-domain reflectometry from a short-circuited termination. The technique is fully compatible with the CMOS technology. To show the feasibility of the idea, two chips are fabricated and tested in a low cost 0.11-μm CMOS process with fT ≈ 80GHz. The full-width at half maximum (FWHM) of the pulses are 6.8 ps and 8.8 ps, and the amplitudes over a 50 load are 0.62 V and 1 V. Either of the chips occupies 1160 × 540μm2 in area.

Reflection-Based Short Pulse Generation in CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205911

**Abstract:**

A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gb/s ultrawideband transceiver fabricated in 28-nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops, one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing is used to control a back-bias-controlled oscillator and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature variations, including skewed process corners. The CR occupies a silicon area of 0.043 mm², locks in less than 1.1 μs, generates an RMS long-term jitter of 6.5 ps, and consumes 1.034 mW while in-lock. This results in an energy value of 0.414 pJ/cycle and a jitter FoM of −224 dB.

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