Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9069.pdf

**Abstract:**

This paper discusses the effect of back-end of line (BEOL) process on cell performance for a Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM). The impact of BEOL is first shown by describing the microscopic evolution of the active Ge-rich GST alloy during process. Ge clustering has been proven to occur during the fabrication process, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is then identified, and an extensive electrical characterization of array performance and reliability is performed on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

ESSCIRC ESSDERC 2021

Improving Ge-rich GST ePCM Reliability Through BEOL Engineering

beol

envm

epcm

reliability

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)** 
Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9171.pdf

**Abstract:**

This paper presents a wide tuning range push-push voltage-controlled oscillator (VCO) at the sub-THz frequency bands. With the introduction of a novel capacitive splitting feedback (CSF) technique and tunable source degeneration (TSD) network, the proposed VCO can simultaneously archive a wide tuning range while maintaining a high output power. The CSF technique improves the oscillation frequency by reducing the effective transistor capacitances, and a wide tuning range is achieved through the TSD network without employing varactors. The proposed VCO is fabricated in a 40-nm digital CMOS process. It shows a -3.5 dBm peak output power with 1.35% DC-to-RF efficiency and a wide tuning range of 10.16% at a center frequency of 267.2 GHz.

A 253-280 GHz Wide Tuning Range VCO with -3.5 dBm Peak Output Power in 40-nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9169.pdf

**Abstract:**

This paper presents a CMOS circular-geometry quad-core voltage-controlled oscillator (VCO) with class-F operation and tail filtering to achieve ultra low phase noise in K band. The use of class-F operation in a circular-geometry multi-core VCO further lowers phase noise but results in new mode ambiguity. We introduce cross-coupled narrow and thin metal traces in the class-F transformer secondary loop to suppress this new mode ambiguity. Also, we extend the circular geometry design to the VCO tail LC filters, reducing the chip area. A proof-of-concept prototype is fabricated in a standard 65 nm CMOS technology. In measurement, the VCO operates from 17.9 to 20.7 GHz. At 19 GHz, the VCO achieves a phase noise of -115 dBc/Hz at 1 MHz offset with a figure of merit (FoM) of -188.4 dBc/Hz.

A 19 GHz Circular-Geometry Quad-Core Tail-Filtering Class-F VCO with -115 dBc/Hz Phase Noise at 1 MHz Offset in 65-nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9310.pdf

**Abstract:**

This paper proposes a periodically time-varying (PTV) inductor applied to a class-D oscillator resulting in a 4.7VDD output swing that effectively improves the phase noise in both 1/f 2 and 1/f 3 regions. Without extra switches, the PTV inductor is realized by reusing the original cross-coupled transistors in the class-D oscillator that semi-periodically cancel the magnetic flux between two coupled inductors. Fabricated in 65nm LP CMOS, the oscillator prototype operating at 0.35V measures FoMs of 192.5±1dBc/Hz at 1MHz offset frequency and 194.6±0.3dBc/Hz at 10MHz offset frequency, over a frequency tuning range from 3.67 to 4.43GHz.

A Periodically Time-Varying Inductor Applied to the Class-D VCO for Phase Noise Improvement

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9176.pdf

**Abstract:**

for automobile applications, a high-switching 48-to-5V DC-DC buck converter is implemented with 0.5μm CMOS process and 0.5μm Gallium-Nitride (GaN)-on-Si process, including the pre-charge tracking technique, temperature-dependent controlled gate driver, and adaptive relaxation gate-drive control technique, which can increase the efficiency by about 8.8% and ensure the current capacity of Enhance-GaN (E-GaN). The inner local negative feedback loop can enhance the reliability and reduce the RON by 12mΩ. The peak efficiency is as high as 95.4%.

A Pre-Charge Tracking Technique in the 40MHz High-Switching 48-to-5V DC-DC Buck Converter with GaN Switches for Reducing Large Self-Commutation Loss and Achieving a High Efficiency of 95.4%

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9148.pdf

**Abstract:**

This paper presents a load-current-regulating OLED driver for wearable light therapy devices. It is based on a single-stage DC-DC hybrid step-up converter architecture achieving high efficiency at a high conversion ratio. The hybrid topology building up the energy through two parallel paths, with an inductor and a capacitor, reduces the loss at a large DC resistance(DCR) of the inductor. Another capacitor reduces switching loss by lowering the voltage stress of switches. The proposed architecture directly regulates the load current without a current-regulation element. 93.21% efficiency is achieved with a large DCR of 200mΩ at a ratio of 4.1.

A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9316.pdf

**Abstract:**

This paper presents a switching supply modulator that enables the implementation of the challenging cyclic-prefix (CP)-length, supply and load tracking times demanded by 5G new radio (NR) applications. To break the tradeoffs among tracking speed, reliability, efficiency and power density, a Δ-T dual-zone hysteretic control is introduced, which allows the S/L tacking and power conversion to be accomplished in a single and compact power stage. A clock-injected switching spectrum regulation scheme stabilizes switching noise spectrum despite of supply, load or process variation. An IC prototype demonstrates a peak efficiency of 95.4% at 10MHz and achieves a power density of 8.9W/mm2, which, to the best of our knowledge, is 3.2 times higher than the best arts reported. It also achieves record-fast S/L tracking at 810ns/V and 327ns/A respectively, with a full power load of 3.45W.

A 8.9W/mm², 95.4%-Efficiency, CP-Length Tracking Switching Supply Modulator for 5G New Radio mm-Wave PA Arrays

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9053.pdf

**Abstract:**

This paper presents an all-paths inductor-connected buck-converter (APICBC). The APICBC balances conduction losses and has continuous paths-currents for high-frequency switching. Efficiency is optimized over a wide load current range due to the adaptive sizing of the power transistors. The converter has three inductors implemented by bond-wire and PCB patterns and operates with a switching frequency of 100 MHz. The maximum efficiency is 81.2%, and the IC is implemented in a 0.18 μm CMOS process.

A 100-MHz 81.2% All-Paths Inductor-Connected Buck-Converter with Balanced Conduction-Losses and Continuous Path-Currents

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9129.pdf

**Abstract:**

This paper demonstrates complementary 2-D FETs based on molybdenum disulfide, Mos₂, as the active film. The n-type (n-FET) and p-type (p-FET) characteristics are obtained from undoped and Nb-doped Mos₂, respectively. We have achieved similar output current drives and high on-off current ratios of more than 10^6 for both devices. Based on the proposed Mos₂ FET technology, a complementary metal-oxide-semiconductor (CMOS) inverter circuit with a gain of around 20 and 85% total noise margin at a 3 V supply, is integrated, exhibiting the potential of the proposed technology for thin film applications such as in flexible electronic circuits.

Complementary Two-Dimensional (2-D) MoS₂ FET Technology

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9281.pdf

**Abstract:**

In this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire nMOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9078.pdf

**Abstract:**

The improvement of forming gas anneal (10 % H2 in N2) at 400 °C on electrical properties of Ge/GeOx/Tm2O3/HfO2 gate stacks is investigated. It is found that forming gas anneal effectively suppresses fixed charge density, oxide trap density and interface state density. Hydrogen is demonstrated to efficiently passivate the negative fixed charge density and reduce the global variability of the flatband voltage down to 90 mV over a wafer. A forming gas anneal is also found to reduce equivalent oxide thickness in scaled gate stacks.

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