Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9295.pdf

**Abstract:**

This paper presents a 40.68MHz active rectifier with cycle-based timing control to extend the allowable duration for completely compensating on/off delays of active diodes under different input voltages and load currents. Both supply-independent ramp and low-voltage-stress startup are also developed to maintain high PCE and VCR and ensure rectifier reliability over a wide input range. Implemented in 0.18um CMOS, the proposed fully-integrated rectifier is the first to achieve full delay compensation at 40.68MHz, so the maximum PCE and VCR reach 86% and 96.3%, respectively, which significantly outperform the prior art.

ESSCIRC ESSDERC 2021

A 40.68MHz Active Rectifier with Cycle-Based On/Off-Delay Compensation for Biomedical Implants

wireless power transmission.

delay compensation

cycle-based timing control

biomedical implants

active rectifier

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9063.pdf

**Abstract:**

This paper presents a multi-band direct-conversion receiver with frequency-translated feedback. The forward path includes a low-noise transconductance amplifier followed by four-phase passive mixers which drive baseband amplifiers, and the feedback path employs tunable resistor banks attached to additional four-phase passive mixers, allowing tunable frequency-selective input matching. The receiver operates from 4-31 GHz exhibiting greater than 25 dB gain through 22 GHz and greater than 17 dB gain through 31 GHz. Noise figure is 5.2 to 9.8 dB, rising with frequency; input-referred 1-dB compression point is -17 dBm; and in-band IIP3 is -6.6 dBm. Out-of-band 1-dB blocker compression is greater than -12 dBm. The receiver core consumes 91 mW, whereas an integrated 2:1 frequency divider and pass-gate buffer for generating non-overlapping four-phase clocks consumes an additional 87-227~mW from 4-31 GHz, respectively.

A 4-31GHz Direct-Conversion Receiver Employing Frequency-Translated Feedback

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9274.pdf

**Abstract:**

We present a tunable LNA for software defined radio based on a compact, tunable transmission line (CTTL) element. The CTTL acts as a passive, widely tunable LC resonance in a cascoded, common source LNA to implement an instantaneously narrowband, multi-octave tunable LNA. The resulting circuit, fabricated in 65nm CMOS, is tunable from 3.5- 20GHz, and consumes 12 mW with gain >12dB, ≥−9.6dBV in-band P1dB, and OOB B1dB up to 31dB higher than the in-band B1dB due to the CTTL-tuned LC filtering. The CTTL-tuned LNA represents a more blocker-tolerant approach to achieving high frequency, software-defined LNAs without significant com- promises in other LNA performance metrics.

A Low Power, 3.5-20GHz Tunable LNA with Out-of-Band Blocker Filtering Based on Compact, Tunable Transmission Line (CTTL) Resonators in 65nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9135.pdf

**Abstract:**

This paper reports a 45-GHz low-noise amplifier (LNA) covering 22.2% –1-dB fractional bandwidth (BW). The transformer-based magnetically-coupling resonators with the gain response staggering techniques are exploited to improve its BW efficiency and gain flatness. Moreover, the 3-coil transformer-based gm-boosting common-gate scheme is utilized as the input matching network to improve the noise figure. The prototype fabricated in a 65-nm CMOS process demonstrates a maximum gain of 30.5 dB and minimum noise figure of 4.1 dB, the –3-dB BW is 15 GHz, and the –1-dB BW is 10 GHz fully covering the band range for IEEE 802.11aj. The LNA consumes 63.6-mW power with a 1.2-V supply and occupies an area of 0.47 mm × 1.00 mm.

A 35-to-50 GHz CMOS Low-Noise Amplifier with 22.2% –1-dB Fractional Bandwidth and 30.5-dB Maximum Gain for 5G New Radio

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9111.pdf

**Abstract:**

Current millimetre-wave (mmW) 5G NR standard supports multiple bands at 24.5/28/37/39/43/47GHz for communications. To cover several bands of the 5G NR and reaching lower end of unlicensed 60GHz band for 802.11ad, This work presents a wideband phased array front-end with LNA and two VGAs for scalar-only weighting function, and a wideband combining network of each signal weight in mmW domain for beamforming. In this work, two array elements are combined in two cascaded stages for extremely wideband operation. Combined load resonances are distributed and adjusted appropriately in each of the combining stages to achieve a flat response over the band of 38.5-60.5GHz. A single array path achieves rms gain of 8.5-12.5dB, noise figure of 6.2-8.1dB, and IP1dB of -33 to -26dBm. The measurements show ~ 6dB of array gain when the two phased array elements are combined in phase with +0.6dB to -0.4dB maximum gain error in the mmW VGAs. The prototype is implemented using 28nm CMOS.

A 38.5-to-60.5 GHz LNA with Wideband Combiner Supporting Cartesian Beamforming Architecture

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9237.pdf

**Abstract:**

This articledescribes the design of Trans-Impedence Ampli er (TIA), which preform a channel select ltering in the base band section for 5G-oriented transceiver. The design of TIA is based on Operational Transconductance Ampli er with parallel R-C feedback. The design is optimized to get stability and achieve high loop gain over an extended bandwidth. In this way, the linearity is guaranteed for extended frequency range. The employed solution is to design an OTA using an auxiliary path called Feed-Forward path which introduce a left-half-plane zero to compensate the negative phase shift introduced by the poles of the main path.

A 17 mW 33 dBm IB-OIP3 0.5-1.5 GHz Bandwidth TIA Based on an Inductor-Stabilized OTA

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9044.pdf

**Abstract:**

This work presents a discrete-time (DT) delta sigma modulator (DSM) ADC that uses ring amplifiers to relax critical speed and efficiency bottlenecks. The DSM is designed as a 3rd-order Cascade of Integrator with Feed Forward (CIFF) with a 4-bit quantizer, and it achieves a peak SNDR of 67dB and DR of 70.0dB with 47.5MHz bandwidth when clocked at 950MHz. This is the highest bandwidth reported to-date among single-channel DT DSM ADCs and demonstrates a viable alternative to continuous-time (CT) DSM ADCs for wideband oversampling applications. With a power consumption of 4.7mW from a 1V supply, FOMS and FOMW are 167.0dB and 27.0fJ/c.s. respectively, demonstrating efficient DT delta-sigma conversion with high bandwidth.

A 47.5MHz BW 4.7mW 67dB SNDR Ringamp Based Discrete-Time Delta Sigma ADC

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9217.pdf

**Abstract:**

This paper presents a high-bandwidth, high-resolution continuous-time incremental sigma-delta modulator employing a finite impulse response (FIR) filter in the feedback for improved clock jitter immunity. The paper proposes a new scheme to alleviate the aggressive overshoots in the incremental regime. Besides, the presented design features a new implementation technique for the dual-RTZ approach in FIR resistive DACs to eliminate inter-symbol interference (ISI) errors. The presented prototype is fabricated in 180-nm CMOS technology and achieves a dynamic range (DR) of 90.3 dB and a peak spurious-free DR of 93.1 dB at a Nyquist conversion rate of 1 MS/s.

A 93.1-dB SFDR, 90.3-dB DR, and 1-MS/s CT Incremental Sigma-Delta Modulator Incorporating a Resistive Dual-RTZ FIR DAC

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9263.pdf

**Abstract:**

This paper presents a dual-mode, multi-bit, second-order oversampling ADC, which can be configured into Sigma-Delta (SD) mode or Incremental (I) mode for interfacing a single or multiple sensors in multi-sensor platforms for automotive applications. Implemented in a 130-nm CMOS technology, the proposed ADC uses only 0.4µm devices and operates at 2.5-V supply in order to be connected to high-voltage sensors, at the cost of intrinsic lower efficiency. The device achieves a maximum SNDR of 63.0 dB and 56.4 dB in the two modes, respectively, with a bandwidth of 2.1 MHz. By reducing the bandwidth to 1.25 MHz in SD-mode a SNR of 73.2 dB is achieved. In both operating modes, the ADC is clocked at 80 MHz, consuming 2.6 mA.

A Dual-Mode Second-Order Oversampling Analog-to-Digital Converter

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9180.pdf

**Abstract:**

This work presents a scaling-friendly Discrete-Time (DT) 2nd order ΔΣ ADC using a passive switched capacitor (SC) integrator and a novel VCO-Frequency Delta-Sigma Modulator (FDSM). The proposed VCO-FDSM employs a linear VCO with negative feedback. A novel all-digital frequency quantizer quantizes the VCO frequency into a multi-bit output with inherent dynamic element matching (DEM) property, which provides the 1st order mismatch noise shaping in the feedback DAC. The passive SC integrator at the input provides an additional order of noise shaping to the VCO-FDSM. This highly digital architecture facilitates a trade-off between the supply voltage and the operational bandwidth (BW) and makes the design suitable for energy-efficient IoT applications. The test chip fabricated in 65nm CMOS technology operates at the supply voltages ranging from 0.6 V to 1.2 V and achieves a 75.7dB peak SNR in 3.5kHz BW, consuming 7.78 uW with a FoMs of 162.2dB at a 1V supply voltage.

A 0.6-to-1.2 V Scaling Friendly Discrete-Time OTA-Free ΔΣ-ADC for IoT Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9086.pdf

**Abstract:**

This work presents a boost converter with time-based control to reduce the controller area and RHP-zero elimination to increase the maximum bandwidth with no extra off-chip component. A PFM operation with seamless PFM to CCM transition increases the light-load efficiency. The prototype converter, implemented in a BCD technology with 0.18um CMOS, shows a bandwidth increase of factor 5 with respect to a standard boost converter. The measured peak efficiency is 96%. The controller has an area occupation of 0.16 square millimeters with a quiescent current of 300uA.

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