Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9336128

**Abstract:**

Generative Adversarial Networks (GAN) consists of multiple deep neural networks cooperating and competing each other. Due to their complex architectures, training GANs requires huge computations and external memory accesses. However, retraining GANs with user-specific data is critical on mobile devices because the pretrained model outputs distorted images under user-specific conditions. This paper proposes an FPGAbased GAN training accelerator to enable energy-efficient domain specific optimization of GAN with user’s local data. A SELRET(Selective-Layer Retraining) is proposed to reduce the computation by 69% through selecting layers that are effective in enhancing the quality of the output. Moreover, ROLIN (Reordering Layers for Instance Normalization) is proposed to reduce the external memory accesses of intermediate data. The design is implemented on Intel’s Cyclone V, showing 51 GFLOPS peak performance with 10.04GFLOPS/W energy-efficiency for face modification of 256×256 image.

ESSCIRC ESSDERC 2021

An Energy-Efficient GAN Accelerator with On-Chip Training for Domain Specific Optimization

generative adversarial network(gan)

fpga

deep learning

The Conference on Uncertainty in Artificial Intelligence (UAI) is one of the premier international conferences on research related to knowledge representation, learning, and reasoning in the presence of uncertainty. It is supported by the [Association for Uncertainty in Artificial Intelligence (AUAI).](https://www.auai.org/)

The 37th Conference on Uncertainty in Artificial Intelligence (UAI 2021) is held fully online. We have an exciting program consisting of keynote talks by [Susan Murphy](https://www.auai.org/uai2021/program?block=A), [Eric Horvitz](https://www.auai.org/uai2021/program?block=B), [Lenka Zdeborová](https://www.auai.org/uai2021/program?block=C), [Judea Pearl](https://www.auai.org/uai2021/program?block=D) and [Ankur Moitra](https://www.auai.org/uai2021/program?block=E), a town hall meeting, peer-reviewed papers, and three workshops. The main conference is single-track and each paper is show-cased with a live component (either a live discussion and Q&A, or a live lightning talk). All papers are also featured in video presentations and in poster sessions in gather.town. The three parallel workshops on Friday allow for smaller meetings on current topics.

The walkthrough video below shows how you can navigate this site and use the different possibilities for interaction: UAIsland2021 on gather.town for posters and social interactions, the mementor platform for virtual mentoring sessions, and the chat and Q&A systems for discussions about talks and posters.

Have a great UAI 2021! 
<br>
<br>Cassio de Campos and Marloes Maathuis
<br>UAI 2021 Program Chairs
<br>uai2021programchairs@gmail.com

<figure class="video_container">
  <iframe src="https://screencast-o-matic.com/watch/cri0lsViAGK?v=6&ff=1&title=0&controls=1" width=526  height=226  frameborder="0" allowfullscreen="true"> </iframe>
</figure>


A ticket is required to access this conference. Please use the provided link to register for the event.

https://auai.org/uai2021/registration

UAI 2021

The Conference on Uncertainty in Artificial Intelligence (UAI) is one of the premier international conferences on research related to knowledge representation, learning, and reasoning in the presence of uncertainty. It is supported by the [Association for Uncertainty in Artificial Intelligence (AUAI).](https://www.auai.org/)

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





This letter presents a RISC-V System-on-Chip (SoC) with fully integrated switched-capacitor DC–DC converters, adaptive clock generators, mixed-precision floating-point vector accelerators, a 5-Gb/s serial memory interface, and an integrated power management unit (PMU) manufactured in 28-nm FD-SOI. The vector accelerator improves performance and energy per task on a matrix multiplication kernel by 15x and 13x, respectively, and end-to-end performance on machine learning and graph analytical workloads by 8x–12x. Inclusion of microarchitectural counters and fine spatial power-domain granularity facilitate the predictive power-management algorithms that reduce energy per task by 13%–22% compared to the baseline scalar processor. System level simulations of a range of SoC architectural variations with multiple cores and vector accelerators complement the silicon measurements.

Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9214.pdf

**Abstract:**

We will present major advances in Time of Flight image sensors for consumer applications. Several innovative elements integrated into a 130nm front side illumination CMOS node reveal superior sensor performance so far only attributed to much more complex backside illumination technologies. The gate controlled pixels comprising deep trenches, buried mirrors and integrated prisms, reveal high quantum efficiency and modulation transfer function close to the physical pixel size. In-pixel common mode suppression prevents saturation even under backlight conditions. The comprehensive System on Chip integrates high speed ADCs, a flexible phase shifter, as well as current monitoring for laser safety.

Advancements in Indirect Time of Flight Image Sensors in Front Side Illuminated CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9072.pdf

**Abstract:**

Dark Count Rate (DCR) in Single-Photon Avalanche Diodes (SPAD) in Complementary Metal-Oxide Semiconductor technology is characterized and analyzed with a comprehensive simulation methodology. Based on a series of measurements of SPAD with various architectures, on an extended range of voltages and temperatures, the DCR measurements are correlated to the spatial localization of traps within the device and their parameters. To this aim, process and electrical simulations using Technology Computer-Aided Design (TCAD) tools are combined with an in-house McIntyre solver to compute the breakdown probability (Pt). The traps are accounted for using thermal SRH carrier generation-recombination mechanism which is coupled with the position-dependent breakdown probability. This rigorous methodology makes it possible to directly compare with DCR measurements, since only generated carriers with a non-negligible avalanche probability are considered.

Dark Count Rate in Single-Photon Avalanche Diodes: Characterization and Modeling Study

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9005.pdf

**Abstract:**

A novel sun sensor concept is presented. Photodiodes operating as solar cells with continuous operation and dedicated logic to calculate the centroid position are integrated to achieve lower latency and energy consumption. The output data flow is remarkably reduced because the centroid of the illuminated pixels is the only sensor output data. It overcomes conventional digital sun sensors based on Active Pixel Sensor (APS) pixels and Address Event Representation (AER) in terms of latency and power consumption. Its latency is in the order of microseconds with an average power consumption lower than 100 uW. Experimental results are provided and benchmarked.

A High-Speed Low-Power Sun Sensor with Solar Cells and Continuous Operation

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9212.pdf

**Abstract:**

The goal of this work is the design, realization, and characterization of a pixel-level front-end in 0.15μm CMOS technology, that allows to directly convert in the digital domain the weak output signal from the Field-Effect Transistor (FET) TeraHertz (THz) detector, in a noise-efficient way. The chosen architecture is a Continuous-Time Sigma-Delta Incremental Analog-to-Digital Converter (CT ΣΔ IADC) with a current DAC feedback, chopper technique and digital lock-in modulation. The measured SNR of this interface is 67.45dB, corresponding to an equivalent number of bit (ENOB) of 10.91. The pixel readout area is 0.072mm2, and the power consumption is 65μW from 1.8V supply. The Noise Equivalent Power (NEP) of the THz detector and readout chain is 268pW/√𝐇𝐳. The readout channel Input Referred Noise (IRN) is 1.2μVrms with the FET, and 0.94μVrms for the channel without detector.

A 0.94-μVrms Input Noise Pixel-Level Continuous Time ΣΔ IADC Interface for THz Sensing

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9146537

**Abstract:**

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16 × 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-B Booth Multiplier in 16-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9177177

**Abstract:**

A 10nm DNN inference accelerator compresses model size with tabulation hash-based fine-grained weight sharing and increases 8b-compute density by 3.4× to 1.6 TOPS/mm2. The compressed model DNN implements lightweight hashing circuits to compress fully connected and recurrent neural networks. Optimized shared weight address generation reduces MUX tree area overhead by 40%. Runtime hash table generation and weight mapping circuits enable a peak energy efficiency of 9.0TOPS/W at 450mV, 25°C. A 128×-compressed 3-layer LSTM classifies TIMIT phonemes with 85.6% accuracy for a total energy of 14µJ/classification, with <0.5% degradation in accuracy over an uncompressed network.

A 9.0TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10nm FinFET CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9134388

**Abstract:**

A 10nm compute-near-memory (CNM) accelerator augments SRAM with multiply accumulate units (MACs) to reduce interconnect energy and achieve 2.9 8b-TOPS/W for matrix-vector computation. The CNM provides high memory bandwidth by accessing SRAM sub-arrays to enable low-latency, real-time inference in fully connected and recurrent neural networks with small mini-batch sizes. For workloads with greater arithmetic intensity such as large-batch convolutional neural networks, the CNM reconfigures into a 2D systolic array to amortize memory access energy over a greater number of computations. Variable-precision 8b/4b/2b/1b MACs increase throughput by up to 8× for binary operations at 33.0 1b-TOPS/W.

A 2.9-33.0 TOPS/W Reconfigurable 1D/2D Compute-Near-Memory Inference Accelerator in 10nm FinFET CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9153788

**Abstract:**

A processing-in-memory (PIM)-based accelerator is presented in 65-nm CMOS for on-chip learning in spiking neural network using timing-based stochastic spike-timing-dependent plasticity (STDP). The design uses mixed-signal processing in the 8T-SRAM array for spike accumulation and all-digital computation for neuron dynamics and synaptic weight updates. The 0.39-mm2 and 14.83-mW test chip demonstrates 100K images/second learning rate and 148.3 nJ/image learning energy.

Processing-In-Memory-Based On-Chip Learning with Spike-Time-Dependent Plasticity in 65-nm CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178725

**Abstract:**

This paper presents a redistributable capacitive power converter for batteryless optically-powered Internet-of-Things (IoT) devices. The proposed converter employs redistributable two-stage charge pump along with a storage capacitor to power milli-watt order low-power RF power amplifier occasionally using indoor light illumination. The first stage tracks the maximum power point of PV cell and stores the energy to the storage capacitor. The second stage further boosts the output to 1.5 V with voltage regulation. The proposed capacitive converter is composed of 16 1.5×/2× reconfigurable charge pump submodules and a digital low dropout regulator (DLDO) to adapt 0.45 to 0.9 V PV input with high efficiency. The submodules are redistributed among two stages according to operating mode to reduce 46.7% on-chip capacitors. The proposed capacitive power converter is fabricated in 0.18 μm CMOS process. The measured results demonstrate the peak power conversion efficiency is 91%, 63.8%, and 68.5% under 1×, 1.5×, and 2× conversion ratios, respectively.

An Energy-Efficient GAN Accelerator with On-Chip Training for Domain Specific Optimization

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